Data Sheet

212
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
17.4 Signal Description
Not applicable.
17.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
17.5.1 I/O Lines
Not applicable.
17.5.2 Power Management
The WDT can continue to operate in any sleep mode where the selected source clock is running. The WDT interrupts
can be used to wake up the device from sleep modes. The events can trigger other operations in the system without
exiting sleep modes. Refer to “PM – Power Manager” on page 117 for details on the different sleep modes.
17.5.3 Clocks
The WDT bus clock (CLK_WDT_APB) is enabled by default, and can be enabled and disabled in the Power Manager.
Refer to “PM – Power Manager” on page 117 for details.
A generic clock (GCLK_WDT) is required to clock the WDT. This clock must be configured and enabled in the Generic
Clock Controller before using the WDT. Refer to “GCLK – Generic Clock Controller” on page 95 for details.
This generic clock is asynchronous to the user interface clock (CLK_WDT_APB). Due to this asynchronicity, accessing
certain registers will require synchronization between the clock domains. Refer to “Synchronization” on page 217 for
further details.
GCLK_WDT is intended to be sourced from the clock of the internal ultra-low-power (ULP) oscillator. Due to the ultra-
low-power design, the oscillator is not very accurate, and so the exact time-out period may vary from device to device.
This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out periods used
are valid for all devices. For more information on ULP oscillator accuracy, consult the “Ultra Low Power Internal 32kHz
RC Oscillator (OSCULP32K) Characteristics” on page 975.
GCLK_WDT can also be clocked from other sources if a more accurate clock is needed, but at the cost of higher power
consumption.
17.5.4 DMA
Not applicable.
17.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the WDT interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 34 for details.
17.5.6 Events
Not applicable.
17.5.7 Debug Operation
When the CPU is halted in debug mode, the WDT will halt normal operation. If the WDT is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. The WDT can be forced to halt operation during debugging.