Data Sheet

211

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181G–SAM-D21_Datasheet–09/2015

17. WDT – Watchdog Timer

17.1 Overview

The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover

from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is

constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset. An

early-warning interrupt is available to indicate an upcoming watchdog time-out condition.

The window mode makes it possible to define a time slot (or window) inside the total time-out period during which the

WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will be

issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be cleared

frequently.

When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a CPU-

independent clock source.The WDT will continue operation and issue a system reset or interrupt even if the main clocks

fail.

17.2 Features

z Issues a system reset if the Watchdog Timer is not cleared before its time-out period

z Early Warning interrupt generation

z Asynchronous operation from dedicated oscillator

z Two types of operation:

z Normal mode

z Window mode

z Selectable time-out periods, from 8 cycles to 16,000 cycles in normal mode or 16 cycles to 32,000 cycles in window

mode

z Always-on capability

17.3 Block Diagram

Figure 17-1. WDT Block Diagram

GCLK_WDT

COUNT

Reset

PER/WINDOW/EWOFFSET

CLEAR

0xA5

Early Warning Interrupt