Data Sheet

209
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
16.8.20 DPLL Status
Name: DPLLSTATUS
Offset: 0x50
Reset: 0x00
Property: -
z Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 3 – DIV: Divider Enable
0: The reference clock divider is disabled.
1: The reference clock divider is enabled.
z Bit 2 – ENABLE: DPLL Enable
0: The DPLL is disabled.
1: The DPLL is enabled.
z Bit 1 – CLKRDY: Output Clock Ready
0: The DPLL output clock is off
1: The DPLL output clock in on.
z Bit 0 – LOCK: DPLL Lock Status
0: The DPLL Lock signal is cleared.
1: The DPLL Lock signal is asserted.
Bit 76543210
DIV ENABLE CLKRDY LOCK
AccessRRRRRRRR
Reset00000000