Data Sheet

208
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bits 10:8 – LTIME[2:0]: Lock Time
These bits select Lock Timeout.
Table 16-15. Lock Time
z Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 5:4 – REFCLK[1:0]: Reference Clock Selection
These bits select the CLK_FDPLL96M_REF source.
Table 16-16. Reference Clock Selection
z Bit 3 – WUF: Wake Up Fast
0: DPLL CK output is gated until complete startup time and lock time.
1: DPLL CK output is gated until startup time only.
z Bit 2 – LPEN: Low-Power Enable
0: The time to digital converter is selected.
1: The time to digital converter is not selected, this will improve power consumption but increase the output jitter.
z Bits 1:0 – FILTER[1:0]: Proportional Integral Filter Selection
These bits select the DPLL filter type.
Table 16-17. Proportional Integral Filter Selection
LTIME[2:0] Name Description
0x0 DEFAULT No time-out
0x1-0x3 Reserved
0x4 8MS Time-out if no lock within 8 ms
0x5 9MS Time-out if no lock within 9 ms
0x6 10MS Time-out if no lock within 10 ms
0x7 11MS Time-out if no lock within 11 ms
REFCLK[1:0] Name Description
0x0 XOSC32 XOSC32 clock reference
0x1 XOSC XOSC clock reference
0x2 GCLK_DPLL GCLK_DPLL clock reference
0x3 Reserved
FILTER[1:0] Name Description
0x0 DEFAULT Default filter mode
0x1 LBFILT Low bandwidth filter
0x2 HBFILT High bandwidth filter
0x3 HDFILT High damping filter