Data Sheet

207
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
16.8.19 DPLL Control B
Name: DPLLCTRLB
Offset: 0x4C
Reset: 0x00000000
Property: Write-Protected
z Bits 31:27 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 26:16 – DIV[10:0]: Clock Divider
These bits are used to set the XOSC clock source division factor. Refer to “Principle of Operation” on page 158.
z Bits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 12 – LBYPASS: Lock Bypass
0: Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1: Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
z Bit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 3130292827262524
DIV[10:8]
AccessRRRRRR/WR/WR/W
Reset00000000
Bit 2322212019181716
DIV[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
LBYPASS LTIME[2:0]
Access R R R R/W R R/W R/W R/W
Reset00000000
Bit 76543210
REFCLK[1:0] WUF LPEN FILTER[1:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000