Data Sheet

200
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Table 16-13. Prescaler Select
z Bits 11:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 9 – CEN: Clock Enable
0: The BOD33 sampling clock is either disabled and stopped, or enabled but not yet stable.
1: The BOD33 sampling clock is either enabled and stable, or disabled but not yet stopped.
Writing a zero to this bit will stop the BOD33 sampling clock.
Writing a one to this bit will start the BOD33 sampling clock.
z Bit 8 – MODE: Operation Mode
0: The BOD33 operates in continuous mode.
1: The BOD33 operates in sampling mode.
z Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 6 – RUNSTDBY: Run in Standby
0: The BOD33 is disabled in standby sleep mode.
1: The BOD33 is enabled in standby sleep mode.
z Bit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
PSEL[3:0] Name Description
0x0 DIV2 Divide clock by 2
0x1 DIV4 Divide clock by 4
0x2 DIV8 Divide clock by 8
0x3 DIV16 Divide clock by 16
0x4 DIV32 Divide clock by 32
0x5 DIV64 Divide clock by 64
0x6 DIV128 Divide clock by 128
0x7 DIV256 Divide clock by 256
0x8 DIV512 Divide clock by 512
0x9 DIV1K Divide clock by 1024
0xA DIV2K Divide clock by 2048
0xB DIV4K Divide clock by 4096
0xC DIV8K Divide clock by 8192
0xD DIV16K Divide clock by 16384
0xE DIV32K Divide clock by 32768
0xF DIV64K Divide clock by 65536