Data Sheet

197
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
16.8.12 DFLL48M Multiplier
Name: DFLLMUL
Offset: 0x2C
Reset: 0x00000000
Property: Write-Protected
z Bits 31:26 – CSTEP[5:0]: Coarse Maximum Step
This bit group indicates the maximum step size allowed during coarse adjustment in closed-loop mode. When
adjusting to a new frequency, the expected output frequency overshoot depends on this step size.
z Bits 25:16 – FSTEP[9:0]: Fine Maximum Step
This bit group indicates the maximum step size allowed during fine adjustment in closed-loop mode. When adjust-
ing to a new frequency, the expected output frequency overshoot depends on this step size.
z Bits 15:0 – MUL[15:0]: DFLL Multiply Factor
This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency. Writing
to the MUL bits will cause locks to be lost and the fine calibration value to be reset to its midpoint.
Bit 3130292827262524
CSTEP[5:0] FSTEP[9:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
FSTEP[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
MUL[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
MUL[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000