Data Sheet

195
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscilla-
tor is disabled if no peripheral is requesting the clock source.
z Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the DFLL behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If DFLLCTRL.ONDEMAND is one, the clock source will be
running when a peripheral is requesting the clock. If DFLLCTRL.ONDEMAND is zero, the clock source will always
be running in standby sleep mode.
z Bit 5 – USBCRM: USB Clock Recovery Mode
0: USB Clock Recovery Mode is disabled.
1: USB Clock Recovery Mode is enabled.
z Bit 4 – LLAW: Lose Lock After Wake
0: Locks will not be lost after waking up from sleep modes if the DFLL clock has been stopped.
1: Locks will be lost after waking up from sleep modes if the DFLL clock has been stopped.
z Bit 3 – STABLE: Stable DFLL Frequency
0: FINE calibration tracks changes in output frequency.
1: FINE calibration register value will be fixed after a fine lock.
z Bit 2 – MODE: Operating Mode Selection
0: The DFLL operates in open-loop operation.
1: The DFLL operates in closed-loop operation.
z Bit 1 – ENABLE: DFLL Enable
0: The DFLL oscillator is disabled.
1: The DFLL oscillator is enabled.
Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value
written to DFLLCTRL.ENABLE will read back immediately after written.
z Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.