Data Sheet

172
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
16.8.2 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected
z Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 17 – DPLLLTO: DPLL Lock Timeout Interrupt Enable
0: The DPLL Lock Timeout interrupt is disabled.
1: The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock
Timeout Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout
interrupt.
z Bit 16 – DPLLLCKF: DPLL Lock Fall Interrupt Enable
0: The DPLL Lock Fall interrupt is disabled.
1: The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall
Interrupt flag is set.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
DPLLLTO DPLLLCKF
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS
Access R/W R R R R/W R/W R/W R/W
Reset00000000
Bit 76543210
DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000