Data Sheet

171
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bit 0 – XOSCRDY: XOSC Ready Interrupt Enable
0: The XOSC Ready interrupt is disabled.
1: The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Inter-
rupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt.