Data Sheet

158
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
The XOSC source can be divided inside the FDPLL96M. The user must make sure that the programmable clock divider
and XOSC frequency provides a valid CLK_FDPLL96M_REF clock frequency that meets the FDPLL96M input frequency
range.
The output clock of the FDPLL96M is CLK_FDPLL96M. The state of the CLK_FDPLL96M clock only depends on the
FDPLL96M internal control of the final clock gater CG.
The FDPLL96M requires a 32kHz clock from the GCLK when the FDPLL96M internal lock timer is used. This clock must
be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to “GCLK – Generic Clock
Controller” on page 95 for details.
16.6.8.2 Block Diagram
Figure 16-2. FDPLL96M Block Diagram
16.6.8.3 Principle of Operation
The task of the FDPLL96M is to maintain coherence between the input reference clock signal (CLK_FDPLL96M_REF)
and the respective output frequency CK via phase comparison. The FDPLL96M supports three independent sources of
clocks XOSC32K, XOSC and GCLK_DPLL. When the FDPLL96M is enabled, the relationship between the reference
clock (CLK_FDPLL96M_REF) frequency and the output clock (CLK_FDPLL96M) frequency is defined below.
Where LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, f
ckrx
is the frequency of
the selected reference clock and f
ck
is the frequency of the FDPLL96M output clock. As previously stated a clock divider
exist between XOSC and CLK_FDPLL96M_REF. The frequency between the two clocks is defined below.
Table 16-3. Generic Clock Input for FDPLL96M
Generic Clock FDPLL96M
FDPLL96M 32kHz clock GCLK_DPLL_32K for internal lock timer
FDPLL96M GCLK_DPLL for CLK_FDPLL96M_REF
TDC
Digital
Filter
DCO
÷N
XOSC32K
XOSC
CK
%JWJEFS
GCLK_DPLL
$(
CLK_FDPLL96M
User
Interface
CLK_FDPLL96M_REF
GCLK_DPLL_32K
f
clk_fdp ll96m
f
clk_fdpll96m_ref
LDR 1
LDRFRAC
16
----------------------------
++
⎝⎠
⎛⎞
×=
f
clk_fd pll96m_ref
f
xosc
1
2 DIV 1+()×
----------------------------------
⎝⎠
⎛⎞
×=