Data Sheet

156
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Following Software sequence should be followed while using the same.
1. load "DFLL48M COARSE CAL" from “NVM User Row Mapping” on page 30 in DFLL.COARSE register
2. Set DFLLCTRL.BPLCKC bit
3. Start DFLL close loop
This procedure will reduce DFLL Lock time to DFLL Fine lock time.
Frequency Locking
The locking of the frequency in closed-loop mode is divided into two stages. In the first, coarse stage, the control logic
quickly finds the correct value for DFLLVAL.COARSE and sets the output frequency to a value close to the correct
frequency. On coarse lock, the DFLL Locked on Coarse Value bit (PCLKSR.DFLLLOCKC) in the Power and Clocks
Status register will be set.
In the second, fine stage, the control logic tunes the value in DFLLVAL.FINE so that the output frequency is very close to
the desired frequency. On fine lock, the DFLL Locked on Fine Value bit (PCLKSR.DFLLLOCKF) in the Power and Clocks
Status register will be set.
Interrupts are generated by both PCLKSR.DFLLLOCKC and PCLKSR.DFLLLOCKF if INTENSET.DFLLOCKC or
INTENSET.DFLLOCKF are written to one.
CLK_DFLL48M is ready to be used when the DFLL Ready bit (PCLKSR.DFLLRDY) in the Power and Clocks Status
register is set, but the accuracy of the output frequency depends on which locks are set. For lock times, refer to the
“Electrical Characteristics” on page 935.
Frequency Error Measurement
The ratio between CLK_DFLL48M_REF and CLK48M_DFLL is measured automatically when the DFLL48M is in closed-
loop mode. The difference between this ratio and the value in DFLLMUL.MUL is stored in the DFLL Multiplication Ratio
Difference bit group(DFLLVAL.DIFF) in the DFLL Value register. The relative error on CLK_DFLL48M compared to the
target frequency is calculated as follows:
Drift Compensation
If the Stable DFLL Frequency bit (DFLLCTRL.STABLE) in the DFLL Control register is zero, the frequency tuner will
automatically compensate for drift in the CLK_DFLL48M without losing either of the locks. This means that
DFLLVAL.FINE can change after every measurement of CLK_DFLL48M.
The DFLLVAL.FINE value overflows or underflows can occur in close loop mode when the clock source reference drifts
or is unstable. This will set the DFLL Out Of Bounds bit (PCLKSR.DFLLOOB) in the Power and Clocks Status register.
To avoid this error, the reference clock in close loop mode must be stable, an external oscillator is recommended and
internal oscillator forbidden. The better choice is to use an XOSC32K.
Reference Clock Stop Detection
If CLK_DFLL48M_REF stops or is running at a very low frequency (slower than CLK_DFLL48M/(2 * MUL
MAX
)), the DFLL
Reference Clock Stopped bit (PCLKSR.DFLLRCS) in the Power and Clocks Status register will be set. Detecting a
stopped reference clock can take a long time, on the order of 2
17
CLK_DFLL48M cycles. When the reference clock is
stopped, the DFLL48M will operate as if in open-loop mode. Closed-loop mode operation will automatically resume if the
CLK_DFLL48M_REF is restarted. An interrupt is generated on a zero-to-one transition on PCLKSR.DFLLRCS if the
DFLL Reference Clock Stopped bit (INTENSET.DFLLRCS) in the Interrupt Enable Set register is set.
16.6.7.2 Additional Features
Dealing with Delay in the DFLL in Closed-Loop Mode
The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M can be up to
several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in the DFLL48M locking
mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the
ERROR
DIFF
MUL
--------------
=