Data Sheet

141
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
15.8.10 APBC Mask
Name: APBCMASK
Offset: 0x20
Reset: 0x00010000
Property: Write-Protected
z Bits 31:21 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 21 – AC1: AC1 APB Clock Enable
0: The APBC clock for the AC1 is stopped.
1: The APBC clock for the AC1 is enabled.
z Bit 20 – I2S: I2S APB Clock Enable
0: The APBC clock for the I2S is stopped.
1: The APBC clock for the I2S is enabled.
z Bit 19 – PTC: PTC APB Clock Enable
0: The APBC clock for the PTC is stopped.
1: The APBC clock for the PTC is enabled.
z Bit 18 – DAC: DAC APB Clock Enable
0: The APBC clock for the DAC is stopped.
1: The APBC clock for the DAC is enabled.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AC1 I2S PTC DAC AC ADC
Access R R R/W R/W R/W R/W R/W R/W
Reset00000001
Bit 151413121110 9 8
TC7 TC6 TC5 TC4 TC3 TCC2 TCC1 TCC0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS PAC2
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000