Data Sheet

134
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
15.8.6 APBC Clock Select
Name: APBCSEL
Offset: 0x0B
Reset: 0x00
Property: Write-Protected
z Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 2:0 – APBCDIV[2:0]: APBC Prescaler Selection
These bits define the division ratio of the APBC clock prescaler (2
n
).
Table 15-10. APBC Prescaler Selection
Bit 76543210
APBCDIV[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
APBCDIV[2:0] Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV4 Divide by 4
0x3 DIV8 Divide by 8
0x4 DIV16 Divide by 16
0x5 DIV32 Divide by 32
0x6 DIV64 Divide by 64
0x7 DIV128 Divide by 128