Data Sheet

115
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 3:0 – ID[3:0]: Generic Clock Generator Selection
These bits select the generic clock generator on which the division factor will be applied, as shown in Table 14-12.
A power reset will reset the GENDIV register for all IDs, including the generic clock generator used by the RTC. If a
generic clock generator ID other than generic clock generator 0 is not a source of a ‚“locked” generic clock or a source of
the RTC generic clock, a user reset will reset the GENDIV for this ID.
After a power reset, the reset value of the GENDIV register is as shown in
Table 14-13.
Table 14-11. Division Factor
Generator Division Factor Bits
Generic clock generator 0 8 division factor bits - DIV[7:0]
Generic clock generator 1 16 division factor bits - DIV[15:0]
Generic clock generators 2 5 division factor bits - DIV[4:0]
Generic clock generators 3 - 8 8 division factor bits - DIV[7:0]
Table 14-12. Generic Clock Generator Selection
Values
Description
0x0 Generic clock generator 0
0x1 Generic clock generator 1
0x2 Generic clock generator 2
0x3 Generic clock generator 3
0x4 Generic clock generator 4
0x5 Generic clock generator 5
0x6 Generic clock generator 6
0x7 Generic clock generator 7
0x8 Generic clock generator 8
0x9-0xF Reserved