Data Sheet

1100
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Figure A-9. I2S Timing PDM2 Mode
SCK input
SD input
Left Right
Left Right
Left
Right
t
PDM2RS
t
PDM2RH
t
PDM2LS
t
PDM2LH
Table A-51. I2S Timing Characteristics and Requirements (Device Variant A)
Symbol Description Mode
V
DD
=1.8V V
DD
=3.3V
UnitsMin. Typ. Max. Min. Typ. Max
t
M_MCKOR
I2S MCK rise
time
(3)
Master mode / Capacitive
load CL = 15 pF
10.0 4.7 ns
t
M_MCKOF
I2S MCK fall time
(3)
Master mode / Capacitive
load CL = 15 pF
12.1 5.3 ns
d
M_MCKO
I2S MCK duty cycle Master mode 45.4 50.0 45.4 50.0 %
d
M_MCKI
I2S MCK duty cycle
Master mode, pin is input
(1b)
50.0 50.0 %
t
M_SCKOR
I2S SCK rise time
(2)
Master mode / Capacitive
load CL = 15 pF
9.7 4.6 ns
t
M_SCKOF
I2S SCK fall time
(3)
Master mode / Capacitive
load CL = 15 pF
10.2 4.5 ns
d
M_SCKO
I2S SCK duty cycle Master mode 45.6 50.0 45.6 50.0 %
f
M_SCKO
1/t
M_SCKO
I2S SCK frequency
Master mode
Supposing external device
response delay is 30ns
7.8 9.5 MHz
f
S_SCKI
1/t
S_SCKI
I2S SCK frequency
Slave mode
Supposing external device
response delay is 30ns
14.4 14.8 MHz
d
S_SCKO
I2S SCK duty cycle Slave mode 50.0 50.0 %
t
M_FSOV
FS valid time Master mode 4.1 4.0 ns
t
M_FSOH
FS hold time Master mode -0.9 -0.9 ns
t
S_FSIS
FS setup time Slave mode 2.3 1.5 ns
t
S_FSIH
FS hold time Slave mode 0.0 0.0 ns
t
M_SDIS
Data input setup
time
Master mode 36.2 24.5 ns
t
M_SDIH
Data input hold
time
Master mode -8.2 -8.2 ns