Data Sheet

1097
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
A.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table A-49. FDPLL96M Characteristics
(1)
(Device Variant A)
Table A-50. FDPLL96M Characteristics
(1)
(Device Variant B)
I
OSC8M
Current consumption
IIDLE IDLE2 on OSC32K versus IDLE2 on
calibrated OSC8M enabled at 8MHz
(FRANGE=1, PRESC=0)
- 64 96 A
t
STARTUP
Startup time
I
- 2.4 3.3 µs
Duty Duty cycle
I
- 50 - %
Symbol Parameter Conditions Min. Typ. Max. Units
Symbol Parameter Conditions Min. Typ. Max. Units
f
IN
Input frequency 32 - 2000 KHz
f
OUT
Output frequency 48 - 96 MHz
I
FDPLL96M
Current consumption
f
IN
= 32 kHz, f
OUT
= 48 MHz 500 700
A
f
IN
= 32 kHz, f
OUT
= 96 MHz 900 1200
Jp Period jitter
f
IN
= 32 kHz, f
OUT
= 48 MHz - 1.5 2.0
%
f
IN
= 32 kHz, f
OUT
= 96 MHz 3.0 10.0
f
IN
= 2 MHz, f
OUT
= 48 MHz 1.3 2.0
f
IN
= 2 MHz, f
OUT
= 96 MHz 3.0 7.0
t
LOCK
Lock Time
After startup, time to get lock
signal.
f
IN
= 32 kHz, f
OUT
= 96 MHz
1.3 2 ms
f
IN
= 2 MHz, f
OUT
= 96 MHz 25 50 s
Duty Duty cycle 40 50 60 %
Symbol Parameter Conditions Min. Typ. Max. Units
f
IN
Input frequency 32 - 2000 KHz
f
OUT
Output frequency 48 - 96 MHz
I
FDPLL96M
Current consumption
f
IN= 32 kHz, fOUT
= 48 MHz 500 740
A
f
IN
= 32 kHz, f
OUT
= 96 MHz 900 1262
Jp Period jitter
f
IN
= 32 kHz, f
OUT
= 48 MHz - 1.5 2.5
%
f
IN
= 32 kHz, f
OUT
= 96 MHz 4.0 10.5
f
IN= 2 MHz, fOUT
= 48 MHz 1.6 2.5
f
IN
= 2 MHz, f
OUT
= 96 MHz 4.6 11.0