Data Sheet

108
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
A power reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the corre-
sponding ID is zero and the ID is not the RTC, a user reset will reset the CLKCTRL register for this ID.
After a power reset, the reset value of the CLKCTRL register versus module instance is as shown in Table 14-5.
0x13 GCLK_SERCOMx_SLOW SERCOMx_SLOW
0x14 GCLK_SERCOM0_CORE SERCOM0_CORE
0x15 GCLK_SERCOM1_CORE SERCOM1_CORE
0x16 GCLK_SERCOM2_CORE SERCOM2_CORE
0x17 GCLK_SERCOM3_CORE SERCOM3_CORE
0x18 GCLK_SERCOM4_CORE SERCOM4_CORE
0x19 GCLK_SERCOM5_CORE SERCOM5_CORE
0x1A GCLK_TCC0, GCLK_TCC1 TCC0,TCC1
0x1B GCLK_TCC2, GCLK_TC3 TCC2,TC3
0x1C GCLK_TC4, GCLK_TC5 TC4,TC5
0x1D GCLK_TC6, GCLK_TC7 TC6,TC7
0x1E GCLK_ADC ADC
0x1F GCLK_AC_DIG AC_DIG
0x20 GCLK_AC_ANA AC_ANA
0x21 GCLK_DAC DAC
0x22 GCLK_PTC PTCReserved
0x23 GCLK_I2S_0 I2S_0
0x24 GCLK_I2S_1 I2S_1
0x25-0x3F Reserved
Table 14-5. CLKCTRL Reset Value after a Power Reset
Module Instance Reset Value after Power Reset
CLKCTRL.GEN CLKCTRL.CLKEN CLKCTRL.WRTLOCK
RTC 0x00 0x00 0x00
WDT 0x02
0x01 if WDT Enable bit in NVM
User Row written to one
0x00 if WDT Enable bit in NVM
User Row written to zero
0x01 if WDT Always-On bit in
NVM User Row written to one
0x00 if WDT Always-On bit in
NVM User Row written to zero
Others 0x00 0x00 0x00
Table 14-4. Generic Clock Selection ID (Continued)
Value Name Description