Data Sheet

1072
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
A.5 Power Consumption
The values in Table A-9 are measured values of power consumption under the following conditions, except where noted:
z Operating conditions
z V
VDDIN
= 3.3V
z Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
z Oscillators
z XOSC32K (32kHz crystal oscillator) stopped
z XOSC (crystal oscillator) running with external 32MHz clock on XIN
z DFLL48M stopped
z Clocks
z XOSC used as main clock source, except otherwise specified
z CPU, AHB clocks undivided
z APBA clock divided by 4
z APBB and APBC bridges off
z The following AHB module clocks are running: NVMCTRL, APBA bridge
z All other AHB clocks stopped
z The following peripheral clocks running: PM, SYSCTRL, RTC
z All other peripheral clocks stopped
z I/Os are inactive with internal pull-up
z CPU is running on flash with 1 wait states
z Cache enabled
z BOD33 disabled
f
GCLK_SERCOM4_CORE
SERCOM4 input clock frequency 48 MHz
f
GCLK_SERCOM5_CORE
SERCOM5 input clock frequency 48 MHz
f
GCLK_TCC0, GCLK_TCC1
TCC0, TCC1 input clock frequency 96 MHz
f
GCLK_TCC2, GCLK_TC3
TCC2,TC3 input clock frequency 48 MHz
f
GCLK_TC4, GCLK_TC5
TC4, TC5 input clock frequency 96 MHz
f
GCLK_TC6, GCLK_TC7
TC6,TC7 input clock frequency 48 MHz
f
GCLK_ADC
ADC input clock frequency 48 MHz
f
GCLK_AC_DIG
AC digital input clock frequency 48 MHz
f
GCLK_AC_ANA
AC analog input clock frequency 64 kHz
f
GCLK_DAC
DAC input clock frequency 350 kHz
f
GCLK_PTC
PTC input clock frequency 48 MHz
f
GCLK_I2S_0
I2S serial 0 input clock frequency 13 MHz
f
GCLK_I2S_1
I2S serial 1 input clock frequency 13 MHz
Table A-8. Maximum Peripheral Clock Frequencies (Device Variant B) (Continued)
Symbol Description Max. Units