Data Sheet

1070
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
f
GCLK_EVSYS_CHANNEL_9
EVSYS channel 9 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_10
EVSYS channel 10 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_11
EVSYS channel 11 input clock frequency 48 MHz
f
GCLK_SERCOMx_SLOW
Common SERCOM slow input clock
frequency
48 MHz
f
GCLK_SERCOM0_CORE
SERCOM0 input clock frequency 48 MHz
f
GCLK_SERCOM1_CORE
SERCOM1 input clock frequency 48 MHz
f
GCLK_SERCOM2_CORE
SERCOM2 input clock frequency 48 MHz
f
GCLK_SERCOM3_CORE
SERCOM3 input clock frequency 48 MHz
f
GCLK_SERCOM4_CORE
SERCOM4 input clock frequency 48 MHz
f
GCLK_SERCOM5_CORE
SERCOM5 input clock frequency 48 MHz
f
GCLK_TCC0, GCLK_TCC1
TCC0,TCC1 input clock frequency 80 MHz
f
GCLK_TCC2, GCLK_TC3
TCC2,TC3 input clock frequency 80 MHz
f
GCLK_TC4, GCLK_TC5
TC4,TC5 input clock frequency 48 MHz
f
GCLK_TC6, GCLK_TC7
TC6,TC7 input clock frequency 48 MHz
f
GCLK_ADC
ADC input clock frequency 48 MHz
f
GCLK_AC_DIG
AC digital input clock frequency 48 MHz
f
GCLK_AC_ANA
AC analog input clock frequency 64 KHz
f
GCLK_DAC
DAC input clock frequency 350 KHz
f
GCLK_PTC
PTC input clock frequency 48 MHz
f
GCLK_I2S_0
I2S serializer 0 input clock frequency 13 MHz
f
GCLK_I2S_1
I2S serializer 1 input clock frequency 13 MHz
Table A-7. Maximum GCLK Generator Output Frequencies (Device Variant B)
Symbol Description Conditions Max. Units
f
GCLKGEN0 / fGCLK_MAIN
GCLK Generator Output Frequency
Undivided 96 MHzf
GCLKGEN1
f
GCLKGEN2
f
GCLKGEN3
Divided 48 MHzf
GCLKGEN4
f
GCLKGEN5
Table A-6. Maximum Peripheral Clock Frequencies (Device Variant A) (Continued)
Symbol Description Max. Units