Data Sheet

1066
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
41.7 Rev. A – 02/2014
Updated V
DD
max from 3.63V to 3.63V in “Absolute Maximum Ratings” on page 935.
Updated VDDIN pin from 57 to 56 in Table 36-2.
“Power Consumption” on page 941: Updated Max values for STANDBYfrom 190.6µA and 197.3µA to 100µA in
Table 36-8.
Added “Peripheral Power Consumption” on page 946.
“I/O Pin Characteristics” on page 950: tRISE and tFALL updated with different load conditions depending on the
DVRSTR value in .
“I/O Pin Characteristics” on page 950: Correct typo IOL and IOH Max values inverted between
PORT.PINCFG.DRVSTR=0 and 1, tRISE and tFALL updated with different load conditions depending on the
DVRSTR value in Table 36-14.
“Analog Characteristics” on page 952: Removed note from Table 36-17.
“Analog-to-Digital (ADC) Characteristics” on page 955: Added Max DC supply current (I
DD
), R
SAMPLE
maximum value
changed from 2.8kW to 3.5kW, Conversion time Typ value change to Min Value in Table 36-21.
“Digital to Analog Converter (DAC) Characteristics” on page 961: Added Max DC supply current (I
DD
) in Table 36-29.
“Analog Comparator Characteristics” on page 963: Added Min and Max values for VSCALE INL, DNL, Offset Error
and Gain Error in Table 36-33.
“Internal 1.1V Bandgap Reference Characteristics” on page 964: Characteristics": Added Min and Max values,
removed accuracy row in Table 36-35.
“SERCOM in I2C Mode Timing” on page 989: Add Typical values for t
R
in Table 36-60.
Removed Asynchronous Watchdog Clock Characterization.
“32.768kHz Internal oscillator (OSC32K) Characteristics” on page 975: Added Max current consumption (I
OSC32K
) in
Table 36-52.
Updated Crystal Oscillator Characteristics (XOSC32K) ESR maximum values, Table 36-45.
Updated Crystal Oscillator Characteristics (XOSC) ESR maximum value, Table 36-47 from 348kΩ to 141kΩ.
“Digital Frequency Locked Loop (DFLL48M) Characteristics” on page 973: Updated presentation, now separating
between Open- and Closed Loop Modes. Added f
REF
Min and Max values to Table 36-50.
Updated typical Startup time ( t
STARTUP
) from 6.1µs to 8µs in Table 36-49.
Updated typical Fine lock time (t
LFINE
) from 700µs to 600µs in Table 36-49.
“Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics” on page 976: Added Current consumption
(I
FDPLL96M
), Period Jitter (Jp), Lock time (t
LOCK
), Duty cycles parameters in Table 36-55.
Added “USB Characteristics” on page 985.
“Timing Characteristics” on page 986: Added SCK period (t
SCK
) Typ value in Table 36-59.
Errata
Errata for revision B added.
Initial revision