Data Sheet

1063
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Added figure Figure 15-2.
Register Summary:
Removed CFD bit from INTENCLR, INTENSET and INTFLAG.
Added PTC bit to APBCMASK register.
Register Description:
AHB Mask register (AHBMASK): Full bit names updated.
APBC Mask register (APBCMASK.PTC): Added PTC to bit 19.
CFD bit removed from INTENCLR, INTENSET and INTFLAG.
“SYSCTRL – System Controller” on page 148
Updated description of “8MHz Internal Oscillator (OSC8M) Operation” on page 154.
FDPLL96M section reorganized and more integrated in the SYSCTRL chapter: Features, Signal Description and
Product Dependencies sub sections removed and integrated with the corresponding sections in SYSCTRL.
Register Summary: Added VREG register on address 0x3C - 0x3D.
Register Description:
Updated reset values in OSC8M.
Updated CALIB[11:0] bit description in OSC8M.
Updated LBYPASS bit description in DPLLCTRLB.
“WDT – Watchdog Timer” on page 211
Updated description in “Principle of Operation” on page 213: Introducing the bits used in Table 17-1 WDT Operating
Modes.
Updated description in “Initialization” on page 213.
Updated description in “Normal Mode” on page 214.
Updated description in “Window Mode” on page 215.
Updated description in “Interrupts” on page 216.
WEN bit description in the Control register (CTRL.WEN) updated with information on enable-protection.
“RTC – Real-Time Counter” on page 229
“Periodic Events” on page 234: Bit names updated fro, PERx to PEREOx in example, Figure 18-4.
CLOCK.HOUR[4:0]: Updated Table 18-10
Mode 0 and Mode 2: CMPx bit renamed to CMP0 since only one CMP0 is available.
Bit description of CLOCK.HOUR[4:0]: Updated Table 18-10 Hour.
ALARMn register renamed to ALARM0.
“DMAC – Direct Memory Access Controller” on page 272
Updated block diagram, Figure 19-1.
General updated description.
“EIC – External Interrupt Controller” on page 336
Register Summary and Register Description:
EVCTRL register: Added bits EXTINTO17 and EXTINTO16 in bit position 17 and 16 respectively.
INTENCLR, INTENSET, INTFLAG registers: Added bits EXTINT17 and EXTINT16 in bit position 17 and 16
respectively.
WAKEUP register: Added bits WAKEUPEN17 and WAKEUPEN16 in bit position 17 and 16 respectively.
CONFIG2 register added, CONFIG0 and CONFIG1 registers updated: Added bits FILTEN0...31 and SENSE0...31.
“NVMCTRL – Non-Volatile Memory Controller” on page 355