Data Sheet

1062
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
41.5 Rev. C – 07/2014
41.6 Rev. B – 07/2014
“Electrical Characteristics” on page 935
Updated condition for Rise time for both SDA and SCL (t
R
) in High Speed Mode: C
b
changed from 1000pF to 100pF
in Table 36-60.
Errata
Errata for revision C and E added.
General:
Introduced the new product family name: Atmel | SMART
Removed references to Clock Failure Detection.
Sub sections within chapters might been moved to other location within the chapter.
Typo corrections.
“Configuration Summary” on page 3
Added 32KB Flash and 4KB SRAM options to SAM D21J and SAM D21G.
“Ordering Information” on page 5
Added Tray to Carrier Type option for SAM D21E, SAMD 21G and SAMD21J ordering codes.
“I/O Multiplexing and Considerations” on page 21 :
Updated REF function on PA03 and PA04 in Table 6-1:
PA03: DAC/VREFP changed to DAC/VREFA.
PA04: ADC VREFP changed to ADC/VREFB.
Updated COM function on PA30 and PA31:
PA30: CORTEX_M0P/SWCLK changed to SWCKL.
PA31: Added SWDIO.
“Memories” on page 29
Added a second note to Table 9-2.
Added Figure 9-1 Calibration and Auxiliary Space.
Added default values for fuses in Table 9-4 NVM User Row Mapping.
“Processor And Architecture” on page 33
MTB renamed from “Memory Trace Buffer” to “Micro Trace Buffer”.
“DSU – Device Service Unit” on page 50
Updated description of “ Starting CRC32 Calculation” on page 57.
Updated titile of Table 12-6 Available Features When Operated From The External Address Range and Device is
Protected.
Added Device Selection table (Table 12-8) to Device Selection bit description the Device Identification register
(DID.DEBVSEL).
“GCLK – Generic Clock Controller” on page 95
Signal names updated in Device Clocking Diagram, Figure 14-1.
“PM – Power Manager” on page 117