Data Sheet
1053
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
39.2.1.1 DSU
1 - The MBIST ""Pause-on-Error"" feature is not functional on SAM D series. Errata
reference: 14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
39.2.1.2 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a write access to a
DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL
module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values
during the locking sequence, an out of bounds interrupt will be generated. These interrupts
will be generated even if the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and
Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt.
3 - The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be
wrong after a USB suspend state. Errata reference: 11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode.
39.2.1.3 NVMCTRL
1 - The NVMCTRL.INTFLAG.READY bit is not updated after a RWWEEER command and will
keep holding a 1 value. If a new RWWEEER command is issued it can be accepted even if
the previous RWWEEER command is ongoing. The ongoing NVM RWWEER will be aborted,
the content of the row under erase will be unpredictable. Errata reference: 13588
Fix/Workaround:
Perform a dummy write to the page buffer right before issuing a RWWEEER command. This will
make the INTFLAG.READY bit behave as expected.
2 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134
This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong
address corresponding to NVM area.
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
3 - When external reset is active it causes a high leakage current on VDDIO. Errata
reference: 13446
Fix/Workaround: