Data Sheet

104
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
14.8.1 Control
Name: CTRL
Offset: 0x0
Reset: 0x00
Property: Write-Protected, Write-Synchronized
z Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: There is a reset operation ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the GCLK to their initial state after a power reset, except for generic
clocks and associated generators that have their WRTLOCK bit in CLKCTRL read as one.
Refer to Table 14-9 for details on GENCTRL reset.
Refer to Table 14-13 for details on GENDIV reset.
Refer to Table 14-5 for details on CLKCTRL reset.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
Bit 76543210
SWRST
AccessRRRRRRRR/W
Reset00000000