Data Sheet

1032
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
11 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up
from sleep. An External Reset, Power on Reset or Watch Dog Reset will start
the device again. Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
device. The average power consumption of the device will increase with 20uA
compared to numbers in the electrical characteristics chapter.
12 - While the internal startup is not completed, PA07 pin is driven low by
the chip. Then as all the other pins it is configured as an High Impedance
pin. Errata reference: 12118
Fix/Workaround:
None
13 - Digital pin outputs from Timer/Counters, AC (Analog Comparator),
GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not change
value during standby sleep mode. Errata reference: 12537
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep mode
in order to keep digital pin output enabled. This is done by setting the RUNSTDBY
bit in the VREG register.
14 - The voltage regulator in low power mode is not functional at
temperatures above 85C. Errata reference: 12291
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
15 - If the external XOSC32K is broken, neither the external pin RST nor the
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
39.1.2.2 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU will
be held in ""CPU Reset Extension"" after any upcoming reset event. Errata
reference: 12015