Data Sheet

1024
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
12 - If the external XOSC32K is broken, neither the external pin RST nor the
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
39.1.1.1 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU will
be held in ""CPU Reset Extension"" after any upcoming reset event. Errata
reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by writing a
one in the DSU STATUSA.CRSTEXT register or by applying an external reset
with SWCLK high or by power cycling the device.
2 - The MBIST ""Pause-on-Error"" feature is not functional on SAM D series.
Errata reference: 14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
39.1.1.2 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
39.1.1.3 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata
reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
39.1.1.4 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a
write access to a DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.