Data Sheet

Registers description LIS3DH

32/42 Doc ID 17530 Rev 1

8.12 CTRL_REG5 (24h)

8.13 CTRL_REG6 (25h)

8.14 REFERENCE/DATACAPTURE (26h)

HR High resolution output mode: Default value: 0

(0: High resolution disable; 1: High resolution Enable)

ST1-ST0 Self test enable. Default value: 00

(00: Self test disabled; Other: See Table 3 4)

SIM SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

Table 34. Self test mode configuration

ST1 ST0 Self test mode

0 0 Normal mode

01Self test 0

10Self test 1

11--

Table 33. CTRL_REG4 description (continued)

Table 35. CTRL_REG5 register

BOOT FIFO_EN -- -- LIR_INT1 D4D_INT1 0 0

Table 36. CTRL_REG5 description

BOOT Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

FIFO_EN FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO Enable)

LIR_INT1 Latch interrupt request on INT1_SRC register, with INT1_SRC register

cleared by reading INT1_SRC itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

D4D_INT1 4D enable: 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set