Instruction Manual

DDR2 Fully Buffered DIMM
Spec Sheet
4 Rev 1.0 Nov. 2010
Pin Description
Symbol Type Description
PS[9:0] Input Primary southbound data, positive lines.
PS#[9:0] Input Primary southbound data, negative lines.
SCK Input System clock input, positive line.
SCK# Input System clock Input, negative line.
SCL Input Serial presence-detect (SPD) clock input.
SS[9:0] Input Secondary southbound data, positive lines.
SS#[9:0] Input Secondary southbound data, negative lines.
PN[13:0] Output Primary northbound data, positive lines.
PN#[13:0] Output Primary northbound data, negative lines.
SN[13:0] Output Secondary northbound data, positive lines.
SN#[13:0] Output Secondary northbound data, negative lines.
SA[2:0] I/O SPD address inputs, also used to select the FBDIMM number in the AMB.
SDA I/O SPD data input/output.
RESET# Supply AMB reset signal.
VCC Supply AMB core power and AMB channel interface power (1.5V).
VDD Supply DRAM power and AMB DRAM I/O power (1.8V).
VDDSPD Supply SPD/AMB SMBUS power (3.3V).
VSS Supply Ground.
VTT Supply DRAM address/command/clock termination power (VDD/2).
M_Test –
The M_Test pin provides an external connection for testing the margin of VREF, which is
pro-duced by a voltage divider on the module. It is not intended to be used in normal system
operation and must not be connected (DNU) in a system. This test pin may have other
fea-tures on future card designs and will be included in this specification at that time.
DNU – Do not use.