Instruction Manual

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DDR2 Fully Buffered DIMM

Spec Sheet

1 Rev 1.0 Nov. 2010

Features

․240-pin, DDR2 Fully Buffered Dual In-line Memory Module (FBDIMM)

․High-speed, 1.5V differential, point-to-point link between the host controller and advanced

memory buffer (AMB)

․SMBus interface to AMB for configuration register access

․VDD = VDDQ = +1.8V,

․VDDSPD = +1.7V to +3.6V,

․VCC = 1.5V for AMB

․Channel fail over mode support

․Programmable CAS Latency: 3, 4, 5

․In-band and out-of-band command access

․MBIST and IBIST Test functions

․Automatic DDR2 SDRAM bus and channel calibration

• Serial presence-detect (SPD) with EEPROM

• Gold edge contacts

Summary of content (6 pages)

PAGE 1
DDR2 Fully Buffered DIMM Spec Sheet Features ․240-pin, DDR2 Fully Buffered Dual In-line Memory Module (FBDIMM) ․High-speed, 1.5V differential, point-to-point link between the host controller and advanced memory buffer (AMB) ․SMBus interface to AMB for configuration register access ․VDD = VDDQ = +1.8V, ․VDDSPD = +1.7V to +3.6V, ․VCC = 1.
PAGE 2
DDR2 Fully Buffered DIMM Spec Sheet Module Specification Bandwidth Data Rate Timing (tCL-tRCD-tRP) 1GB (128Mx72) 64Mx8 2Rank With Intel Heat Sink PC2-5300 DDR2-667 5-5-5 PC2-6400 DDR2-800 5-5-5 1GB (128Mx72) 128Mx8 1Rank With Intel Heat Sink PC2-4200 DDR2-533 4-4-4 PC2-5300 DDR2-667 5-5-5 PC2-6400 DDR2-800 5-5-5 2GB (256Mx72) 128Mx8 2Ranks With Intel Heat Sink PC2-4200 DDR2-533 4-4-4 PC2-5300 DDR2-667 5-5-5 PC2-6400 DDR2-800 5-5-5 4GB (512Mx72) 128Mx8 4Ranks With Intel Heat Si
PAGE 3
DDR2 Fully Buffered DIMM Spec Sheet Pin Assignments 240-Pin FBDIMM Front 240-Pin FBDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VDD 31 PN3 61 PN9# 91 PS9# 121 VDD 151 SN3 181 SN9# 211 SS9# 2 VDD 32 PN3# 62 VSS 92 VSS 122 VDD 152 SN3# 182 VSS 212 VSS 3 VDD 33 VSS 63 PN10 93 PS5 123 VDD 153 VSS 183 SN10 213 SS5 4 VSS 34 PN4 64 PN10# 94 PS5# 124 VSS 154 SN4 184 SN10# 214 SS5#
PAGE 4
DDR2 Fully Buffered DIMM Spec Sheet Pin Description Symbol Type Description PS[9:0] Input Primary southbound data, positive lines. PS#[9:0] Input Primary southbound data, negative lines. SCK Input System clock input, positive line. SCK# Input System clock Input, negative line. SCL Input Serial presence-detect (SPD) clock input. SS[9:0] Input Secondary southbound data, positive lines. SS#[9:0] Input Secondary southbound data, negative lines.
PAGE 5
DDR2 Fully Buffered DIMM Spec Sheet DDR2 FBDIMM Module Dimensions (Intel Heat Sink) Note 1: All dimensions are typical unless otherwise stated. (Millimeters) Note 2: The dimensional diagram is for reference only 5 Rev 1.0 Nov.
PAGE 6
DDR2 Fully Buffered DIMM Spec Sheet DDR2 FBDIMM Module Dimensions (Apple Heat Sink) Note 1: All dimensions are typical unless otherwise stated. (Millimeters) Note 2: The dimensional diagram is for reference only 6 Rev 1.0 Nov.