- SPL Digital Dynamics Processor Owner's Manual

Loudness Maximizer

Specifications

(1) AES/EBU is defined for levels from 2V to 7 V

Measurements AES/EBU: 4,4 V with load

(2) S/P-DIF is defined for levels from 200 mV to 700 mV

Measurements S/P-DIF: 500 mV with load

Subject to change without notice.

Input/Output

Sample rate frequency 32-48 kHz, automatic detection

AES/EBU, twisted pair (1), AES 3

AES/EBU in- & output impedance:110 Ohms

S/P-DIF, co-axial (2), SPDIF-2

S/P-DIF input impedance:75 Ohms

Wordclock In/Through, co-axial, BNC

Wordclock in-/output impedance:75 Ohms

MIDI In/Through:yes

RS 232 (PC): yes

RS 422 (MAC,max +/- 14 V):yes

Free download at www.spl-electronics.com

Clip display,Input transformer (AES/EBU),

Output transformer (AES/EBU),Relay Hard Bypass (AES/EBU)

Measurements

AES/EBU: Jitter 1ns

S/P-DIF:Jitter 3 ns

Wordclock In:Jitter 1,5 ns

Power supply

Torroidal transformer,60 VA

Fuse:1A/slow blow

GND-Lift switch: yes

Voltage selector 115 V/230 V

Dimensions: 19"/1U; 482 x 44,45 x 350 mm

Weight: 4,9 kg