User Manual

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USERS MANUAL
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Document number Revision
4/198 17-LXE 108 566 Uen PA6
Figure 7: PCM Timing Diagram
The meaning and value of the timing parameters are described in Table 12.
Name Description Min Typical Max Unit
PCM_SYNC cycle time. 125
µs
t
SYNC
PCM_SYNC frequency 8.0 kHz
t
SYNCA
PCM_SYNC asserted time. 62.4 62.5
µs
t
SYNCD
PCM_SYNC de-asserted time. 62.4 62.5
µs
t
SU(SYN
C)
PCM_SYNC setup time to PCM_CLK rising. 1.95
µs
t
H(SYNC)
PCM_SYNC hold time after PCM_CLK
falling.
1.95
µs
PCM_CLK cycle time. 7.8
µs
t
CLK
PCM_CLK frequency 128 kHz
t
CLKH
PCM_CLK high time. 3.8 3.9
µs
t
CLKL
PCM_CLK low time. 3.8 3.9
µs
t
PDLD
Propagation delay from PCM_CLK rising to
PCM_DLD valid.
50 ns
T
SU(ULD
)
PCM_ULD setup time to PCM_CLK falling. 70 ns
T
H(ULD)
PCM_ULD hold time after PCM_CLK falling. 20 ns
Table 12: PCM Timing Parameters