User Manual

DM15/25 Integrator’s Manual 19 OF 38
4.1.4.2.2 Timing
Timing shall be according to the following diagram (see Figure 4). The signals in the diagram shall
be interpreted according to the following relation.
DM-15/DM-25 signal Diagram name
PCMCLK PCMCLK (output)
PCMSYNC PCMSYN (output)
PCMULD PCMI (input)
PCMDLD PCMO (output)
Figure 4 PCM timing diagram for DM-15/DM-25
The meaning and value of the timing parameters are described in Table 4.
Name Description Min Typ Max Unit
fPCMCLK clock frequency 200 kHz
fPCMSYN PCM clock frequency 8 kHz
tPSS PCMSYN (setup) to PCMCLK (fall) 10 ns
tPSH PCMSYN pulse length 20 ns
tDSL PCMI (setup) to PCMCLK (fall) 10 ns
tDSH PCMI (hold) from PCMCLK (fall) 10 ns
tPDLP PCMO valid from PCMCLK (rise) 25 ns
Table 4 PCM timing parameters for DM-15/DM-25