User Manual

DM15/25 Integrator’s Manual 18 OF 38

Pin DM-15/DM-25 Description

13 PCMCLK External PCM Clock Output

14 PCMSYNC External PCM frame Sync

15 PCMULD External PCM Voice Input

16 PCMDLD External PCM Voice Input

Already defined CMOS output/input electrical characteristics apply (see Section 4.1.2 General

Electrical and Logical Characteristics). The voltage levels at the PCM interface are in accordance

with the 3.3 V DC CMOS technology.

The PCM format (for PCMULD and PCMDLD) follows a linear PCM data format with 13-bit

data embedded in a 16-bit word. The data bits in PCMULD (input) and PCMDLD (output) are

aligned so that the MSB in each word occurs on the same clock edge. See timing diagram in Figure

4.1.4.2.1 Data Format

The DM-15/DM-25 module implements a 13-bit PCM with the 13-bit data embedded in a 16-bit

word as follows. The output data is compatible with the linear PCM data I/O of an industry standard

Texas Instrument DSP.

Each PCM word shall contain 16-bits D0 - D15. D13 - D1 is the 2´s complement value of the 13-bit

PCM, with D13 as the sign bit. D14 and D15 are always set to be equivalent with D13, and D0 can

contain an optional LSB if a 14-bit word is used. D13 is the MSB while D1 is the LSB if a 14-bit

word is not used. Note that the MSB is sent in first place.

Bit Contents

D15 - D14 Equal to D13

D13 – D1 Two complement of the 13-bit PCM

D0 Optional additional data

MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB

= D13 13 bit PCM

16 bit data word