User Guide

75KAV/75KAV-X
59
SDRAM Cycle Length
Time
You can select CAS latency time in HCLKs of 2 or 3.
The system board designer should have set the val-
ues in this field, depending on the DRAM installed.
Do not change the values in this field unless you
change specifications of the installed DRAM or the
installed CPU.
P2C/C2P Concurrency This item allows you to enable/disable the PCI to CPU,
CPU to PCI concurrency.
The choice: Enabled, Disabled.
DRAM Drive Strength Leave this item with Auto mode.
The choice: Auto, Manual.
DRAM Drive Value When “DRAM Drive Strength” is set to “Auto”, this
item will be unable to be selected. We don’t recom-
mend user to adjust this item.
Memory Hole In order to improve performance, certain space in
memory is reserved for ISA cards. This memory must
be mapped into the memory space below 16MB.
The choice: 15M-16M, Disabled.
PCI Master Pipeline
Req
Use default setting.
Fast R-W Turn Around This item controls the DRAM timing. It allows you to
enable / disable the fast read / write turn around.
The choice: Enabled, Disabled.
DRAM Clock This item allows you to control the DRAM speed.
The choice: Host Clock, HCLK+33M.
DRAM Timing by SPD This item allows you to select DRAM Timing by SPD
or not.
SPD (Serial Presence Detect) you can find it located
on your memory modules, BIOS reads information
coded in SPD during system boot up resulting in a
accurate memory operation.
Bank Interleave
The choice: Disabled, 2 Bank, 4 Bank.