user manual

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C 115 Revision 1.91 (08-18-08)
DATASHEET
Figure 14.7 Address Latching for All Modes
PARAMETER MIN TYP MAX UNITS
t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns
t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns
t25 A4-A15, AEN to nLDEV Delay 30 ns
Figure 14.8 Synchronous Write Cycle - nVLBUS=0
t25
t9
t8
Valid
nADS
A
ddress, AEN, nBE[3:0]
nLDEV
t21t21
t11
t17A
t8
t9
t16
t20
t18
t10
Valid
Valid
Clock
A
ddress, AEN, nBE[3:0]
nADS
W/nR
nCYCLE
Write Data
nSRDY