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SMSC LAN91C111 REV C DATASHEET Revision 1.91 (08-18-08)

Datasheet

PRODUCT FEATURES

LAN91C111

10/100 Non-PCI

Ethernet Single Chip

MAC + PHY

 Single Chip Ethernet Controller

 Dual Speed - 10/100 Mbps

 Fully Supports Full Duplex Switched Ethernet

 Supports Burst Data Transfer

 8 Kbytes Internal Memory for Receive and Transmit

FIFO Buffers

 Enhanced Power Management Features

 Optional Configuration via Serial EEPROM Interface

 Supports 8, 16 and 32 Bit CPU Accesses

 Internal 32 Bit Wide Data Path (Into Packet Buffer

Memory)

 Built-in Transparent Arbitration for Slave Sequential

Access Architecture

 Flat MMU Architecture with Symmetric Transmit and

Receive Structures and Queues

 3.3V Operation with 5V Tolerant IO Buffers (See Pin

List Description for Additional Details)

 Single 25 MHz Reference Clock for Both PHY and

MAC

 External 25Mhz-output pin for an external PHY

supporting PHYs physical media.

 Low Power CMOS Design

 Supports Multiple Embedded Processor Host

Interfaces

—ARM

—SH

— Power PC

— Coldfire

— 680X0, 683XX

— MIPS R3000

 3.3V MII (Media Independent Interface) MAC-PHY

Interface Running at Nibble Rate

 MII Management Serial Interface

 128-Pin QFP package; lead-free RoHS compliant

package also available.

 128-Pin TQFP package, 1.0 mm height; lead-free

RoHS compliant package also available.

 Commercial Temperature Range from 0°C to 70°C

(LAN91C111)

 Industrial Temperature Range from -40°C to 85°C

(LAN91C111i)

Network Interface

 Fully Integrated IEEE 802.3/802.3u-100Base-TX/

10Base-T Physical Layer

 Auto Negotiation: 10/100, Full / Half Duplex

 On Chip Wave Shaping - No External Filters

Required

 Adaptive Equalizer

 Baseline Wander Correction

 LED Outputs (User selectable – Up to 2 LED

functions at one time)

—Link

—Activity

— Full Duplex

— 10/100

— Transmit

— Receive

Summary of content (128 pages)

PAGE 1
LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY PRODUCT FEATURES Datasheet Single Chip Ethernet Controller Dual Speed - 10/100 Mbps Fully Supports Full Duplex Switched Ethernet Supports Burst Data Transfer 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers Enhanced Power Management Features Optional Configuration via Serial EEPROM Interface Supports 8, 16 and 32 Bit CPU Accesses Internal 32 Bit Wide Data Path (Into Packet Buffer Memory) Built-in
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ORDER NUMBERS: LAN91C111-NC, LAN91C111i-NC (INDUSTRIAL TEMPERATURE) FOR 128-PIN QFP PACKAGES LAN91C111-NS, LAN91C111i-NS (INDUSTRIAL TEMPERATURE) FOR 128-PIN QFP LEAD-FREE ROHS COMPLIANT PACKAGES LAN91C111-NE (1.0MM HEIGHT); LAN91C111i-NE (INDUSTRIAL TEMPERATURE) FOR 128-PIN TQFP PACKAGES LAN91C111-NU (1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 4 Signal Descriptions . . . . . . . .
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 Bank Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank 0 - Transmit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank 0 - EPH Status Register . . . . . . . . . . . . . . . . . . . . . . .
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chapter 16 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SMSC LAN91C111 REV C 5 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet List of Figures Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3.1 Basic Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3.2 Block Diagram . . . . . . . . . . . . . . . . . . .
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet List of Tables Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package) . . . . . . . . . . . . . . 14 Table 7.1 4B/5B Symbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7.2 Transmit Level Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8.1 Internal I/O Space Mapping . . . . . .
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 1 General Description The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 2 Pin Configurations 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 XTAL2 XTAL1 RX_ER RX_DV RXD0 RXD1 RXD2 RXD3 VDD CRS100 RX25 GND TXD0 TXD1 TXD2 TXD3 COL100 TXEN100 VDD TX25 GND D0 D1 D2 D3 GND D4 D5 D6 D7 VDD nBE3 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LAN91C111FEASTTM 128 PIN TQFP 96 95 94 93
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/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 RX_ER RX_DV RXD0 RXD1 RXD2 RXD3 VDD CRS100 RX25 GND TXD0 TXD1 TXD2 TXD3 COL100 TXEN100 VDD TX25 GND D0 D1 D2 D3 GND D4 D5 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 LAN91C111FEASTTM 128 PIN QFP 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 3 Block Diagrams The diagram shown in Figure 3.1, "Basic Functional Block Diagram", describes the device basic functional blocks. The SMSC LAN91C111 is a single chip solution for embedded designs with minimal Host and external supporting devices required to implement 10/100 Ethernet connectivity solutions.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet EEPROM INTERFACE MII Control Control Control Control Address 8-32 bit Bus Interface Unit Control Arbiter Control TPO Control WR FIFO Data RD FIFO MMU TX/RX FIFO Pointer Ethernet Protocol Handler (EPH) DMA TX Data 8K Byte Dynamically Allocated SRAM 10/100 PHY TXD[0-3] 32-bit Data TPI RX Data 32-bit Data RXD[0-3] Figure 3.2 Block Diagram The diagram shown in Figure 3.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet EECS EESK EEDO EEDI MII External Signals RBIAS EEPROM CONTROL To MII External Signals CSMA/CD TXD[3:0] TX_ER TXEN100 TX25 4B5B ENCODER 100BASE-TX TRANSMITTER MLT3 ENCODER SCRAMBLER SWITCHED CURRENT SOURCE LP FILTER + TPO+ - TPO- CLOCK GEN (PLL) 10BASE-T TRANSMITTER MANCHESTER CRS100 COL100 ROM DAC + LP FILTER - CLOCK GEN (PLL) COLLISION RXD[3:0] RX_ER RX_DV RX25 100BASE-TX RECEIVER SQUELCH +/- Vth MII SERIAL Manage -ment C
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 4 Signal Descriptions Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 5 Description of Pin Functions PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION TQFP QFP 81-92 83-94 Address A4-A15 I** Input. Decoded by LAN91C111 to determine access to its registers. 78-80 80-82 Address A1-A3 I** Input. Used by LAN91C111 for internal register selection. 41 43 Address Enable AEN I** Input. Used as an address qualifier. Address decoding is only enabled when AEN is low.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PIN NO. NAME BUFFER TYPE SYMBOL DESCRIPTION TQFP QFP 42 44 Local Bus Clock LCLK I** Input. Used to interface synchronous buses. Maximum frequency is 50 MHz. Limited to 8.33 MHz for EISA DMA burst mode. This pin should be tied high if it is in asynchronous mode. 38 40 Asynchronous Ready ARDY OD16 Open drain output. ARDY may be used when interfacing asynchronous buses to extend accesses.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION TQFP QFP 9 11 EEPROM Clock EESK O4 Output. 4 μsec clock used to shift data in and out of the serial EEPROM. 10 12 EEPROM Select EECS O4 Output. Serial EEPROM chip select. Used for selection and command framing of the serial EEPROM. 7 9 EEPROM Data Out EEDO O4 Output. Connected to the DI input of the serial EEPROM. 8 10 EEPROM Data In EEDI I with Input.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION TQFP QFP 125 127 Receive Data Valid RX_DV I with pulldown Input from MII PHY. Envelope of data valid reception. Used for receive data framing. 112 114 Collision Detect 100 Mbps COL100 I with pulldown Input from MII PHY. Collision detection input. 113-116 115-118 Transmit Data TXD3TXD0 O12 Outputs. Transmit Data nibble to MII PHY. 109 111 Transmit Clock TX25 I with pullup Input.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 6 Signal Description Parameters This section provides a detailed description of each SMSC LAN91C111 signal. The signals are arranged in functional groups according to their associated function. The ‘n’ symbol at the beginning of a signal name indicates that it is an active low signal. When ‘n’ is not present before the signal name, it indicates an active high signal.
PAGE 20
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 7 Functional Description 7.1 Clock Generator Block 1. The XTAL1 and XTAL2 pins are to be connected to a 25 MHz crystal. 2. TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY). 3. RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and running the receive state machine. (2.
PAGE 21
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 7.4 BIU Block The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one. Transparent latches are added on the address path using rising nADS for latching. When working with an asynchronous bus like ISA, the read and write operations are controlled by the edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle.
PAGE 22
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet The MAC and external PHY communicate via MDIO and MDC of the MII Management serial interface. MDIO:Management Data input/output. Bi-directional between MAC and PHY that carries management data. All control and status information sent over this pin is driven and sampled synchronously to the rising edge of MDC signal. MDC:Management Data Clock. Sourced by the MAC as a timing reference for transfer of information on the MDIO signal.
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SMSC LAN91C111 REV C 23 DATASHEET MDIO MDC MDIO MDC ST[1:0] 0 0 READ CYCLE ST[1:0] 0 0 WRITE CYCLE 1 1 1 1 OP[1:0] 1 2 OP[1:0] 0 2 0 1 3 3 P4 P3 P2 6 PHYAD[4:0] P2 6 PHYAD[4:0] 5 P3 5 P1 7 P1 7 P0 8 P0 8 R4 9 R4 9 R3 R2 11 12 R1 REGAD[4:0] R2 11 R1 12 R0 13 1 15 0 TA[1:0] 14 D15 16 D14 17 D13 18 R0 13 TA[1:0] Z 14 0 15 D15 16 D14 17 D13 18 WRITE BITS PHY CLOCKS IN DATA ON RISING EDGES OF MDC REGAD[4:0] 10 R3 10 WRITE
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 7.5.4 MII Packet Data Communication with External PHY The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the MIl requirements outlined in IEEE 802.3 and shown in Figure 7.2. TX_EN = 1 TX_EN = 0 TX_EN = 0 START IDLE PREAMBLE OF FRAME DELIM. PRMBLE SFD 62 BT 2 BT IDLE DATA NIBBLES DATA 1 DATA 2 DATA N-1 DATA N PREAMBLE = [ 1 0 1 0 ...
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet edges. RXD0 carries the least significant bit and RXD3 the most significant bit of the nibble. RX_DV goes inactive when the last valid nibble of the packet (CRC) is presented at RXD0-RXD3. RX_ER might be asserted during packet reception to signal the LAN91C111 that the present receive packet is invalid. The LAN91C111 will discard the packet by treating it as a CRC error.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ETHERNET MAC FRAME INTERFRAME GAP SFD PREAMBLE DA SA LN LLC DATA FCS LN LLC DATA FCS INTERFRAME GAP 100 BASE-TX DATA SYMBOLS IDLE SSD SFD PREAMBLE IDLE SSD DA SA = [ 1 1 1 1...] = [ 1 1 0 0 0 1 0 0 0 1] ESD IDLE SOI IDLE BEFORE / AFTER 4B5B ENCODING, SCRAMBLING, AND MLT3 CODING PREAMBLE = [ 1 0 1 0 ...
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 1 0 M b ps o p e r a t i o n i s s i m i l a r t o t h e 1 0 0 M b ps T X o p e r a t i o n e x c e p t , ( 1 ) t h e r e i s n o scrambler/descrambler, (2) the encoder/decoder is Manchester instead of 4B5B, (3) the data rate is 10Mbps instead of 100Mbps, and (4) the twisted pair symbol data is two level Manchester instead of ternary MLT-3.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 7.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 7.7.4 Clock and Data Recovery Clock Recovery - 100 Mbps Clock recovery is done with a PLL. If there is no valid data present on the TP inputs, the PLL is locked to the 25 MHz TX25. When valid data is detected on the TP inputs with the squelch circuit and when the adaptive equalizer has settled, the PLL input is switched to the incoming data on the TP input.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet If 25 consecutive descrambled idle pattern 1's are not detected within the 1ms interval, the descrambler goes out of synchronization and restarts the synchronization process. If the descrambler is in the unsynchronized state, the descrambler loss of synchronization detect bit is set in the Ml serial port Status Output register to indicate this condition. Once this bit is set, it will stay set until the descrambler achieves synchronization.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet N B 1.0 0.8 P H 0.6 D 0.4 C I O E Voltage (V) 0.2 0.0 Q A M F R J -0.2 S -0.4 U LK -0.6 W V -0.8 G -1.0 0 10 20 30 40 50 60 70 80 90 100 T 10 TIME (ns) Figure 7.4 TP Output Voltage Template - 10 MBPS REFERENCE TIME (NS) INTERNAL MAU VOLTAGE (V) A 0 0 B 15 1.0 C 15 0.4 D 25 0.55 E 32 0.45 F 39 0 G 57 -1.0 H 48 0.7 I 67 0.6 J 89 0 K 74 -0.55 L 73 -0.55 M 61 0 N 85 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet REFERENCE TIME (NS) INTERNAL MAU VOLTAGE (V) Q 111 0.15 R 111 0 S 111 -0.15 T 110 -1.0 U 100 -0.3 V 110 -0.7 W 90 -0.7 Transmit Level Adjust The transmit output current level is derived from an internal reference voltage and the external resistor on RBIAS pin.
PAGE 33
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet STP (150 Ohm) Cable Mode The transmitter can be configured to drive 150 Ohm shielded twisted pair cable. The STP mode can be selected by appropriately setting the cable type select bit in the PHY MI serial port Configuration 1 register. When STP mode is enabled, the output current is automatically adjusted to comply with IEEE 802.3 levels.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet a. Short Bit 3.1V Slope 0.5 V/ ns 585mV 585 mV sin ( *t/PW) PW 0 b. Long Bit 3.1V Slope 0.5 V/ ns 585mV 585 mV sin (2 * t/PW) 585 mV sin [2 3PW/4 PW/4 0 (t - PW/2)/PW] PW Figure 7.5 TP Input Voltage Template -10MBPS TP Squelch - 100 Mbps The squelch block determines if the TP input contains valid data. The 100 Mbps TP squelch is one of the criteria used to determine link integrity.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Equalizer Disable The adaptive equalizer can be disabled by setting the equalizer disable bit in the PHY Ml serial port Configuration 1 register. When disabled, the equalizer is forced into the response it would normally have if zero cable length was detected. Receive Level Adjust The receiver squelch and unsquelch levels can be lowered by 4.5 dB by setting the receive level adjust bit in the PHY Ml serial port Configuration 1 register.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SSD) is signaled to the controller interface. When False Carrier is detected, the MAC is notified of false carrier and invalid received, and the bad SSD bit is set in the PHY Ml serial port Status Output register. Once a False Carrier Event is detected, the idle pattern (two /I/I/ symbols) must be detected before any new SSD's can be sensed.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0 BT 4.5 BT 3.1 V 0.5 V/ns 0.25 BT 2.25 BT 585 mV 6.0 BT +50 mV -50 mV 45.0 BT 585 mV sin(2 * * (t/1BT)) 0 t 0.25 BT and 2.25 t 2.5 BT -3.1 V 2.5 BT 4.5 BT Figure 7.6 SOI Output Voltage Template - 10MBPS 7.7.12 Link Integrity & AutoNegotiation General The LAN91C111 can be configured to implement either the standard link integrity algorithms or the AutoNegotiation algorithm.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 1.3 BT 0 BT 3.1 V 0.5 V/ns 585 mV 0.5 BT 0.6 BT 2.0 BT 300 mV 4.0 BT +50 mV +50 mV -50 mV 0.25 BT 200 mV -50 mV 4.0 BT 42.0 BT -3.1 V 0.85 BT 2.0 BT Figure 7.7 Link Pulse Output Voltage Template - NLP, FLP 100BASE-TX Link Integrity Algorithm -100Mbps Since 100BASE-TX is defined to have an active idle signal, then there is no need to have separate link pulses like those defined for 10BASE-T.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet a.) Normal Link Pulse (NLP) TPO± b.) Fast Link Pulse (FLP) TPO± D0 Clock D1 Clock Data D2 Clock Data D3 Clock Data D14 Clock Data D15 Clock Data Clock Data Figure 7.8 NLP VS. FLP Link Pulse The AutoNegotiation algorithm is initiated by any of these events: (1) AutoNegotiation enabled, (2) a device enters the Link Fail State, (3) AutoNegotiation Reset.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet device halts all transmissions including link pulses for 1200-1500 ms, enters the Link Fail State, and restarts the negotiation process. When AutoNegotiation mode is turned on or reset, software driver should wait for at least 1500ms to read the ANEG_ACK bit in the MI PHY Status Register to determine whether the AutoNegotiation process has been completed.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Autopolarity Disable The autopolarity feature can be disabled by setting the autopolarity disable bit in the PHY MI serial port Configuration 2 register. 7.7.15 Full Duplex Mode 100 Mbps Full Duplex mode allows transmission and reception to occur simultaneously. When Full Duplex mode is enabled, collision is disabled.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet R/LT bits are also interrupt bits if they are not masked out with the Mask register bits. Interrupt bits automatically latch themselves into their register locations and assert the interrupt indication when they change state. Interrupt bits stay latched until they are read. When interrupt bits are read, the interrupt indication is deasserted and the interrupt bits that caused the interrupt to happen are updated to their current value.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 8 MAC Data Structures and Registers 8.1 Frame Format In Buffer Memory The frame format in memory is similar for the Transmit and Receive areas. The first word is reserved for the status word. The next word is used to specify the total number of bytes, and it is followed by the data area. The data area holds the frame itself. By default, the last byte in the receive frame format is followed by the CRC, and the Control byte follows the CRC.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant. The transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memory. DATA AREA - The data area starts at offset 4 of the packet structure and can extend up to 2043 bytes.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet BROADCAST - Receive frame was broadcast. When a broadcast packet is received, the MULTCAST bit may be also set on the status word in addition to the BRODCAST bit. The software implement may just ignore the MULTCAST bit if for BRODCAST packet. BADCRC - Frame had CRC error, or RX_ER was asserted during reception. ODDFRM - This bit when set indicates that the received frame had an odd number of bytes. TOOLNG - Frame length was longer than 802.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Regardless of the functional description, all registers can be accessed as doublewords, words or bytes. The default bit values upon hard reset are highlighted below each register. Table 8.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Bank 7 is a new register Bank to the SMSC LAN91C111 device. This bank has extended registers that allow the extended feature set of the SMSC LAN91C111. 8.5 Bank 0 - Transmit Control Register OFFSET NAME TYPE SYMBOL 0 TRANSMIT CONTROL REGISTER READ/WRITE TCR This register holds bits programmed by the CPU to control some of the protocol transmit options.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C111 will transmit a preamble pattern the next time a carrier is seen on the line. If a packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal operation.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SQET - Signal Quality Error Test. This bit is set under the following conditions: 1. LAN91C111 is set to operate in Half Duplex mode (SWFDUP=0); 2. When STP_SQET=1 and SWFDUP=0, SQET bit will be set upon completion of a transmit operation and no SQET Pulse has occurred during the IPG (Inter Frame Gap). If a pulse has occurred during the IPG, SQET bit will not get set. 3.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the LAN91C111 will automatically abort a packet being received when the appropriate collision input is activated. This bit has no effect if the SWFDUP bit in the TCR is set. STRIP_CRC - When set, it strips the CRC on received frames. As a result, both the Byte Count and the frame format do not contain the CRC.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.9 Bank 0 - Memory Information Register OFFSET NAME TYPE SYMBOL 8 MEMORY INFORMATION REGISTER READ ONLY MIR HIGH BYTE FREE MEMORY AVAILABLE (IN BYTES * 2K * M) 0 0 0 0 0 1 0 0 1 0 0 MEMORY SIZE (IN BYTES *2K * M) LOW BYTE 0 0 0 0 0 FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Register) and determine the duplex mode. When this bit is set (1), the Internal PHY will operate at full duplex mode. When this bit is cleared (0), the Internal PHY will operate at half Duplex mode.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet WHAT DO YOU WANT TO DO? 10 Full Duplex 10 Half Duplex AUTO-NEGOTIATION CONTROL BITS SPEED AND DUPLEX MODE CONTROL FOR THE PHY DUPLEX MODE CONTROL FOR THE MAC 0 0 0 1 X X 1 0 1 0 1 X X 1 1 0 X X 0 1 1 0 0 0 0 X X 0 0 1 0 0 X X 0 1 0 X X 0 0 0 LS2A, LS1A, LS0A – LED select Signal Enable. These bits define what LED control signals are routed to the LEDA output pin on the LAN91C111 Ethernet Controller.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Reserved – Must be 0. 8.11 Bank 1 - Configuration Register OFFSET NAME TYPE SYMBOL 0 CONFIGURATION REGISTER READ/WRITE CR The Configuration Register holds bits that define the adapter configuration and are not expected to change during run-time. This register is part of the EEPROM saved setup.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.12 Bank 1 - Base Address Register OFFSET NAME TYPE SYMBOL 2 BASE ADDRESS REGISTER READ/WRITE BAR This register holds the I/O address decode option chosen for the LAN91C111. It is part of the EEPROM saved setup and is not usually modified during run-time.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet LOW BYTE ADDRESS 0 0 0 0 0 HIGH BYTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS 1 0 0 0 0 LOW BYTE 0 ADDRESS 2 0 0 0 0 HIGH BYTE 0 ADDRESS 3 0 0 0 0 LOW BYTE 0 ADDRESS 4 0 0 0 0 HIGH BYTE 0 ADDRESS 5 0 8.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.15 Bank 1 - Control Register HIGH BYTE LOW BYTE OFFSET NAME TYPE SYMBOL C CONTROL REGISTER READ/WRITE CTR Reserved RCV_ BAD Reserved Reserved AUTO RELEASE Reserved Reserved Reserved 0 0 0 1 0 0 1 0 LE ENABLE CR ENABLE TE ENABLE Reserved Reserved EEPROM SELECT RELOAD STORE 0 0 0 1 0 0 0 0 RCV_BAD - When set, bad CRC packets are received.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.16 Bank 2 - MMU Command Register OFFSET NAME TYPE SYMBOL 0 MMU COMMAND REGISTER WRITE ONLY BUSY BIT READABLE MMUCR This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet OPERATION CODE DECIMAL VALUE 110 6 ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. 111 7 RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet OFFSET NAME TYPE SYMBOL 3 ALLOCATION RESULT REGISTER READ ONLY ARR This register is updated upon an ALLOCATE MEMORY MMU command. FAILED Reserved 1 0 ALLOCATED PACKET NUMBER 0 0 0 0 0 0 FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the Interrupt Status Register. TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.20 Bank 2 - Data Register OFFSET NAME TYPE SYMBOL 8 THROUGH BH DATA REGISTER READ/WRITE DATA DATA HIGH X X X X X X X X X X X X DATA LOW X X X X DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet MDINT OFFSET NAME TYPE SYMBOL C INTERRUPT ACKNOWLEDGE REGISTER WRITE ONLY IST Reserved RX_OVRN INT TX EMPTY INT TX INT OFFSET NAME TYPE SYMBOL D INTERRUPT MASK REGISTER READ/WRITE MSK MDINT MASK Reserved EPH INT MASK RX_OVRN INT MASK ALLOC INT MASK TX EMPTY INT MASK TX INT MASK RCV INT MASK 0 0 0 0 0 0 0 0 This register can be read and written as a word or as two individual bytes.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet LATCOL - Late Collision 16COL - 16 collisions Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register. 1. 1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error Enable) EPH INT will only be cleared by the following methods: Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK transition.
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SMSC LAN91C111 REV C 65 DATASHEET EPHSR INTERRUPTS MERGED INTO EPH INT TX_SVC TXENA TEMASK CRMASK CTR-ROL LEMASK Edge Detector on Link Err SQET LOST CARR LATCOL 16COL Fatal TX Error TX Complete nWRACK IntAck7 IntAck4 IntAck2 IntAck1 nRDIST nQ D S Q MDINT nQ D S Q RX_OVRN ALLOCATION FAILED nQ D S Q TX FIFO EMPTY nQ D S Q 6 5 4 3 2 1 0 DATA BUS D[15:0] OE D[7:0] Interrupt Status Register 7 RCV FIFO NOT EMPTY 7 6 5 4 3 2 1 0 nOE D[15:8] Interrupt Mask Regist
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.23 HIGH BYTE Bank 3 - Management Interface OFFSET NAME TYPE SYMBOL 8 MANAGEMENT INTERFACE READ/WRITE MGMT Reserved MSK_ CRS100 Reserved Reserved Reserved Reserved Reserved Reserved 0 0 1 1 0 0 1 1 MDOE MCLK MDI MDO 0 0 MDI Pin 0 LOW BYTE Reserved 0 0 1 1 MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0). MDO - MII Management output. The value of this bit drives the MDO pin.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 8.25 Bank 3 - RCV Register OFFSET NAME TYPE SYMBOL C RCV REGISTER READ/WRITE RCV HIGH BYTE LOW BYTE Reserved 0 0 0 0 0 0 0 0 RCV DISCRD Reserved Reserved MBO MBO MBO MBO MBO 0 0 0 1 1 1 1 1 RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being received.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet CYCLE NCSOUT LAN91C111 DATA BUS AEN=0 A3=0 A4-15 matches I/O BASE BANK SELECT = 7 Driven low. Transparently latched on nADS rising edge. Ignored on writes. Tri-stated on reads. BANK SELECT = 4,5,6 High Ignore cycle. Otherwise High Normal LAN91C111 cycle. SMSC LAN91C111 REV C 69 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 9 PHY MII Registers Multiple Register Access Multiple registers can be accessed on a single PHY Ml serial port access cycle with the multiple register access features. The multiple register access features can be enabled by setting the multiple register access enables bit in the PHY Ml serial port Configuration 2 register.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet REGISTER ADDRESS REGISTER NAME 17 Configuration 2 18 Status Output 19 Mask 20 Reserved PHY Register Description Table 9.1 MII Serial Frame Structure
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SYMBOL NAME DEFINITION R/W REGAD[4:0] Register Address If REGAD[4:0] = 00000-11110, these bits determine the specific register from which D[15:0] is read/written. If multiple register access is enabled and REGAD[4:0] = 11111, all registers are read/written in a single cycle.
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SMSC LAN91C111 REV C 4 73 DATASHEET Reserved Mask 19 20 Status Output 18 17 Configuration 2 16 Configuration 1 AutoNegot. Remote Capability AutoNegot.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 9.1 Register 0. Control Register RST LPBK SPEED ANEG_EN PDN MII_DIS ANEG_RST DPLX RW, SC RW RW RW RW RW RW. SC RW 0 0 1 1 0 1 0 0 COLST Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 RST - Reset A ‘1’ written to this bit will initiate a reset of the PHY.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet DPLX - Duplex mode When Auto Negotiation is disabled this bit can be used to manually select the link duplex state. Writing a ‘1’ to this bit selects full duplex while a ‘0’ selects half duplex. When Auto-Negotiation is enabled reading or writing this bit has no effect. COLTST - Collision test Setting a ‘1’ allows for testing of the MII COL signal. ‘0’ allows normal operation. Reserved:Reserved, Must be 0 for Proper Operation 9.2 Register 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet REM_FLT- Remote Fault Detect ‘1’ indicates a Remote Fault. Latches the ‘1’ condition and is cleared by reading this register or resetting the PHY. CAP_ANEG - AutoNegotiation Capable Indicates the ability (‘1’) to perform ANEG or not (‘0’). LINK - Link Status A ‘1’ indicates a valid Link and a ‘0’ and invalid Link. The ‘0’ condition is latched until this register is read. JAB - Jabber Detect Jabber condition detected when ‘1’ for 10Mbps.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet NP - Next Page A ‘1’ indicates the PHY wishes to exchange Next Page information. ACK - Acknowledge It is used by the Auto-negotiation function to indicate that a device has successfully received its Link Partner’s Link code Word. RF - Remote Fault When set, an advertisement frame will be sent with the corresponding bit set.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 9.6 Register 16.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet CABLE Select 0 = Receive Equalizer On (For 100MB Mode Only) Cable Type Select 1 = STP (150 Ohm) 0 = UTP (100 Ohm) RLVL0 TLVL0-3 Receive Input 1 = Receive Squelch Levels Reduced By 4.5 dB R/W Level Adjust 0 = Normal Transmit Output See Table 7.2 Level Adjust TRF0-1 Transmitter 11 = -0.25nS Rise/Fall Time 10 = +0.0nS Adjust 01 = +0.25nS 00 = +0.50nS 9.7 Register 17.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet INTMDIO: Interrupt Scheme Select Reserved: 9.8 0 = No Multiple Register Access 0 = No Multiple Register Access 1 = Interrupt Signaled With MDIO Pulse During Idle 1 = Interrupt Signaled With MDIO Pulse During Idle 0 = Interrupt Not Signaled On MDIO 0 = Interrupt Not Signaled On MDIO Reserved for Factory Use Register 18.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet SSD: Start Of Stream Error 1 = No Start Of Stream Delimiter Detected on Receive Data 0 = Normal ESD: End Of Stream Error 1 = No End Of Stream Delimiter Detected on Receive Data 0 = Normal RPOL: Reverse Polarity Detect 1 = Reverse Polarity Detected JAB: Jabber Detect 1 = Jabber Detected 0 = Normal SPDDET: 100/10 Speed Detect 1 = Device in 100Mbps Mode (100BASE-TX) 0 = Device in 10Mbps Mode (10BASE-T) DPLXDET: Duplex Detect 1 = Device I
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet MLNKFAIL: Interrupt Mask Link Fail Detect 1 = Mask Interrupt For LNKFAIL In Register 18 0 = No Mask MLOSSSYN: MCWRD: Interrupt Mask Descrambler Loss 1 = Mask Interrupt For LOSSSYNC In Register 18 of Synchronization Detect 0 = No Mask Interrupt Mask Codeword Error 1 = Mask Interrupt For CWRD In Register 18 0 = No Mask MSSD: Interrupt Mask Start Of Stream Error 1 = Mask Interrupt For SSD In Register 18 0 = No Mask MESD: Interrupt Mask End
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW 1 0 1 0 0 0 0 0 Reserved:Reserved for Factory Use SMSC LAN91C111 REV C 83 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 10 Software Driver and Hardware Sequence Flow 10.1 Software Driver and Hardware Sequence Flow for Power Management This section describes the sequence of events and the interaction between the Host Driver and the Ethernet controller to perform power management. The Ethernet controller has the ability to reduce its power consumption when the Device is not required to receive or transmit Ethernet Packets.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 10.2 Flow Of Events For Restoring Device In Normal Power Mode S/W DRIVER 1 CONTROLLER FUNCTION Write and set (1) the “EPH Power EN” Bit, located in the configuration register, Bank 1 Offset 0. 2 Ethernet MAC Enables the RX Clock, TX clock derived from the Internal PHY. The EPH Clock is also enabled. 3 Write the PDN bit in PHY MI Register 0 to 0 The PHY is then set in isolation mode (MII_DIS bit is set).
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet S/W DRIVER MAC SIDE 6 7 Upon transmit completion the first word in memory is written with the status word. The packet number is moved from the TX FIFO into the TX completion FIFO. Interrupt is generated by the TX completion FIFO being not empty. If a TX failure occurs on any packets, TX INT is generated and TXENA is cleared, transmission sequence stops. The packet number of the failure packet is presented at the TX FIFO PORTS Register.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet S/W DRIVER MAC SIDE 7 8 The MAC generates a TXEMPTY interrupt upon a completion of a sequence of enqueued packets. If a TX failure occurs on any packets, TX INT is generated and TXENA is cleared, transmission sequence stops. The packet number of the failure packet is presented at the TX FIFO PORTS Register. SERVICE INTERRUPT – Read Interrupt Status Register, exit the interrupt service routine. Option 1) Release the packet.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ISR Save Bank Select & Address Ptr Registers Mask SMC91C111 Interrupts Read Interrupt Register No Yes RX INTR? Yes TX INTR? Call TX INTR or TXEMPTY INTR No Call RXINTR Get Next TX Yes ALLOC INTR? Packet Available for Transmission? No Yes Write Allocated Pkt # into Packet Number Reg. No Call ALLOCATE Write Ad Ptr Reg.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes Destination Multicast? No Read Words 2, 3, 4 from RAM for Address Filtering No No Address Filtering Pass? Status Word OK? Yes Yes Do Receive Lookahead Get Copy Specs from Upper Layer No Okay to Copy? Yes Copy Data Per Upper Layer Specs Issue "Remove and Release" Command Return to ISR Figure 10.2 RX INTR SMSC LAN91C111 REV C 89 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TX Interrupt With AUTO_RELEASE = FALSE 1. Save the Packet Number Register Saved_PNR = Read Byte (Bank 2, Offset 2) 2. Read the EPH Status Register Temp = Read (Bank 0, Offset 2) 3. Acknowledge TX Interrupt Write Byte (0x02, (Bank 2, Offset C)); 4. Check for Status of Transmission If ( Temp AND 0x0001) { //If Successful Transmission Step 4.1.1: Issue MMU Release (Release Specific Packet) Write (0x00A0, (Bank2, Offset 0)); Step 4.1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) TXEMPTY = X & TXINT = 1 (Transmission Failed) TXEMPTY = 1 & TXINT = 0 (Everything went through successfully) Read Pkt.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet D R IV E R S E N D A L L O C ATE C h o o se B a n k S e le ct R e g iste r 2 Issu e "A llo ca te M e m o ry" C o m m a n d to M M U C a ll A L L O C ATE R e a d In te rru p t S ta tu s R e g iste r E xit D rive r S e n d Ye s A llo ca tio n Pa sse d ? No R e a d A llo ca tio n R e su lt R e g iste r W rite A llo ca te d Pa cke t in to Pa cke t # R e g iste r S to re D a ta B u ffe r Po in te r W rite A d d re ss Po in te r R e g iste r C
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet multicast packets that might not be for the node, and that are not subject to upper layer software flow control. INTERRUPT GENERATION The interrupt strategy for the transmit and receive processes is such that it does not represent the bottleneck in the transmit and receive queue management between the software driver and the controller.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet INTERRUPT 'NOT EMPTY' STATUS REGISTER RCV INT TWO PACKET NUMBER RX FIFO PACKET NUMBER REGISTER TX EMPTY INT OPTIONS TX INT ALLOC INT RX FIFO TX FIFO 'EMPTY' RX PACKET NUMBER TX COMPLETION FIFO 'NOT EMPTY' TX DONE PACKET NUMBER CSMA ADDRESS CPU ADDRESS CSMA/CD LOGICAL ADDRESS PACKET # MMU M.S. BIT ONLY PACK # OUT PHYSICAL ADDRESS RAM Figure 10.6 Interrupt Generation for Transmit, Receive, MMU Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 11 Board Setup Information The following parameters are obtained from the EEPROM as board setup information: ETHERNET INDIVIDUAL ADDRESS I/O BASE ADDRESS MII INTERFACE All the above mentioned values are read from the EEPROM upon hardware reset.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C111 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads. Note: If no EEPROM is connected to the LAN91C111, for example for some embedded applications, the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 16 BITS IOS2-0 WORD ADDRESS 000 0h CONFIGURATION REG. 1h BASE REG. 4h CONFIGURATION REG. 5h BASE REG. 8h CONFIGURATION REG. 9h BASE REG. Ch CONFIGURATION REG. Dh BASE REG. 10h CONFIGURATION REG. 11h BASE REG. 14h CONFIGURATION REG. 15h BASE REG. 18h CONFIGURATION REG. 19h BASE REG. 20h IA0-1 21h IA2-3 22h IA4-5 001 010 011 100 101 110 XXX Figure 11.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 12 Application Considerations The LAN91C111 is envisioned to fit a few different bus types. This section describes the basic guidelines, system level implications and sample configurations for the most relevant bus types. All applications are based on buffered architectures with a private SRAM bus. FAST ETHERNET SLAVE ADAPTER Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds. Adapter requires: 1. LAN91C111 chip 2.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.1 VL Local Bus Signal Connections (continued) VL BUS SIGNAL LAN91C111 SIGNAL NOTES D0-D31 D0-D31 32 bit data bus.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet VLBUS W/nR W/nR A2-A15 A2-A15 LCLK LCLK M/nIO AEN nRESET RESET IRQn LAN91C111 INTR0 D0-D31 D0-D31 nRDYRTN nRDYRTN nBE0-nBE3 nBE0-nBE3 nADS nADS Delay 1 LCLK nCYCLE nSRDY nLRDY nLDEV O.C. simulated O.C. nLDEV Figure 12.1 LAN91C111 on VL BUS HIGH-END ISA OR NON-BURST EISA MACHINES On ISA machines, the LAN91C111 is accessed as a 16 bit peripheral. The signal connections are listed in the following table: Table 12.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors (continued) ISA BUS SIGNAL LAN91C111 SIGNAL NOTES nIOWR nWR I/O Write strobe - asynchronous write access. Address is valid before leading edge. Data is latched on trailing edge. IOCHRDY ARDY This signal is negated on leading nRD, nWR if necessary. It is then asserted on CLK rising edge after the access condition is satisfied.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet ISA BUS A1-A15, AEN A1-A15, AEN RESET RESET nBE2, nBE3 VCC D0-D15 D0-D15 LAN91C111 INTR0 IRQ nIORD nRD nIOWR nWR A0 nBE0 nBE1 nSBHE nLDEV nIOCS16 O.C. Figure 12.2 LAN91C111 on ISA BUS EISA 32 BIT SLAVE On EISA the LAN91C111 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path option. As an I/O slave, the LAN91C111 uses asynchronous accesses.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.3 EISA 32 Bit Slave Signal Connections (continued) EISA BUS SIGNAL LAN91C111 SIGNAL Latched W-R combined with nCMD nRD I/O Read strobe - asynchronous read accesses. Address is valid before its leading edge. Must not be active during DMA bursts if DMA is supported. Latched W-R combined with nCMD nWR I/O Write strobe - asynchronous write access. Address is valid before leading edge . Data latched on trailing edge.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 12.3 EISA 32 Bit Slave Signal Connections (continued) EISA BUS SIGNAL LAN91C111 SIGNAL GND A1 NOTES EISA BUS LA2- LA15 A2-A15 RESET RESET AEN AEN M/nIO D0-D31 D0-D31 INTR0 IRQn LAN91C111 nBE[0:3] nCMD nWR nBE[0:3] nRD LATCH + gates nWR LCLK BCLK nSTART nADS nLDEV nEX32 O.C. Figure 12.3 LAN91C111 on EISA BUS Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 13 Operational Description 13.1 Maximum Guaranteed Ratings* Operating Temperature Range 0°C to +70°C for LAN91C111 (-40°C to 85°C for LAN91C111I) Storage Temperature Range -55C° to + 150°C Lead Temperature Range (soldering, 10 seconds) +325°C Positive Voltage on any pin, with respect to Ground VCC + 0.3V Negative Voltage on any pin, with respect to Ground -0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER SYMBOL MIN IIL TYP MAX UNITS COMMENTS -10 +10 µA VIN = 0 IIH -10 +10 µA VIN = VCC IIL -110 μA VIN = 0 +110 μA VIN = VCC 0.4 V IOL = 6 mA V IOH = -4 mA +10 µA VIN = 0 to VCC 0.4 V IOL = 6 mA V IOH = -4 mA +10 µA VIN = 0 to VCC 0.4 V IOL = 20 mA V IOH = -10 mA +10 µA VIN = 0 to VCC 0.4 V IOL = 35 mA V IOH = -15 mA +10 µA VIN = 0 to VCC 0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS 0.4 V IOL = 35 mA V IOH = -15 mA +10 µA VIN = 0 to VCC 0.4 V IOL = 4 mA V na +10 µA VIN = 0 to VCC Dynamic Current (Assuming internal PHY is used) I/O24 Type Buffer Low Output Level VOL High Output Level VOH 2.4 Output Leakage IOL -10 I/OD Type Buffer Low Output Level VOL High Output Level VOH 2.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 13.3 Twisted Pair Characteristics, Transmit VDD = 3.3v +/- 5% RBIAS = 11K +/- 1 %, no load LIMIT SYM Tov PARAMETER TP Differential Output Voltage UNIT CONDITIONS 1.050 Vpk 100 Mbps, UTP Mode, 100 Ohm Load 1.225 1.285 Vpk 100 Mbps, STP Mode, 150 Ohm Load 2.2 2.5 2.8 Vpk 10 Mbps, UTP Mode, 100 Ohm Load 2.694 3.062 3.429 Vpk 10 Mbps, STP Mode, 150 Ohm Load MIN TYP MAX 0.950 1.000 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet LIMIT SYM PARAMETER UNIT MIN TOIR TP Output Current Adjustment Range TYP 0.80 1.2 VDD = 3.3V, Adjustable with RBIAS, relative to TOIA with RBIAS=11K 0.86 1.16 VDD = 3.3V, Adjustable with LVL[3:0] Relative to Value at TLVL[3:0]=1000 TORA TP Output Current TLVL Step Accuracy TOR TP Output Resistance 10K Ohm TOC TP Output Capacitance 15 pF 13.4 CONDITIONS MAX +/-50 % Relative to Ideal Values in Table 3.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 14 Timing Diagrams t2 Address, AEN, nBE[3:0] Valid nADS t3 t4 Read Data Valid t6 t1 t5 nRD, nWR t5A Write Data Valid Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0ns 50ns 100ns Asynchronous Cycle -- Using nADS 150ns 200ns 250 t9 Addr,AEN,nBE[1:0] valid t8 nADS t3 t4 Read Data valid t6 t1 t5 nRD,nWR t5A Write Data valid Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet 0ns 50ns 100ns 150ns 200ns Asynchronous Cycle - nADS=0 250n t2 nDATACS t3A t4 Read Data valid t6A t1A t5 nRD,nWR t5A Write Data D0~D31 valid Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER MIN t26 ARDY Low Pulse Width 100 t26A Control Active to ARDY Low t13 Valid Data to ARDY High t17 t12 t22 TYP MAX UNITS 150 ns 10 ns 10 t18 ns t14 t18 Clock t12A nDATACS t17A W/nR t22A nCYCLE t20 Write Data a t20 t20 b c t15 nRDYRTN Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet t17 t12 t14 Clock t12A nDATACS t17A W/nR nCYCLE t19 Read Data t19 a b c t15 nRDYRTN Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet t8 nADS t9 Address, AEN, nBE[3:0] Valid t25 nLDEV Figure 14.7 Address Latching for All Modes PARAMETER MIN TYP MAX t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t25 A4-A15, AEN to nLDEV Delay 30 UNITS ns t18 t10 t20 Clock t9 Address, AEN, nBE[3:0] Valid t8 nADS t17A t16 W/nR t11 nCYCLE Write Data Valid t21 t21 nSRDY Figure 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER MIN TYP MAX t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t10 nCYCLE Setup to LCLK Rising 5 ns t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns t16 W/nR Setup to nCYCLE Active 0 ns t17A W/nR Hold after LCLK Rising with nSRDY Active 3 ns t18 Data Setup to LCLK Rising (Write) 15 ns t20 Data Hold from LCLK Rising (Write) 4 ns t21 nSRDY Delay fr
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet PARAMETER MIN TYP MAX t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t10 nCYCLE Setup to LCLK Rising 5 ns t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns t16 W/nR Setup to nCYCLE Active 0 ns t20 Data Hold from LCLK Rising (Read) 4 ns t21 nSRDY Delay from LCLK Rising t23 nRDYRTN Setup to LCLK Rising 3 ns t24 nRDYRTN Hold after LCLK Rising 3 ns 7 UNIT
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet AC TEST TIMING CONDITIONS Unless otherwise noted, all test conditions are as follows: 1. VDD = 3.3V +/-5% 2. RBIAS = 11K +/- 1%, no load 3. Measurement Points: 4. TPO±, TPI±: 0.0 V During Data, ±0.3V at start/end of packet 5. All other inputs and outputs: 1.4 Volts Table 14.1 Transmit Timing Characteristics LIMIT SYM PARAMETER MIN t30 Transmit Propagation Delay t31 TYP UNIT CONDITIONS 140 nS 100Mbps 600 nS 10Mbps ±0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 14.2 Receive Timing Characteristics LIMIT SYM PARAMETER MIN t36 t37 TYP Receive Input Jitter SOI Pulse Minimum Width Required for Idle Detection UNIT CONDITIONS ±3.0 nS pk-pk 100Mbps ±13.5 nS pk-pk 10Mbps 200 nS 10Mbps Measure TPI± from last zero cross to 0.3V point MAX 125 t 36 TPI± DATA DATA DATA DATA DATA SOI t 37 Figure 14.12 Receive Timing, End of Packet - 10 MBPS Table 14.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPO± I DATA DATA DATA DATA DATA DATA DATA DATA DATA TPI± I I I I J K DATA DATA DATA DATA t DATA T DATA DATA DATA R I I 38 Collision Observed by Physical Layer t 34 t 35 LEDn MII 10 Mbps TPO± TPI± t 38 Collision Observed by Physical Layer t 34 t 35 LEDn Figure 14.13 Collision Timing, Receive Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPI± I TPO± I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA I I I J K t DATA DATA DATA DATA T R I I 39 Collision Observed by Physical Layer t 34 t 35 LEDn MII 10 Mbps TPI± TPO± t 39 Collision Observed by Physical Layer t 34 t 35 LEDn Figure 14.14 Collision Timing, Transmit SMSC LAN91C111 REV C 121 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet MII 100 Mbps TPO± I I J K t TPO± I I I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA 40 I I J K JAM JAM JAM JAM T R I I I t 41 Collision Observed by Physical Layer MII 10 Mbps TPI± t TPO± 40 JAM JAM JAM JAM Figure 14.15 Jam Timing Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Table 14.4 Link Pulse Timing Characteristics LIMIT SYM UNIT CONDITIONS PARAMETER MIN TYP MAX t42 NLP Transmit Link Pulse Width See Figure 7.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet TPO± t 42 t 43 a.) Transmit NLP TPI± t 44 t 45 t 47 t 46 LEDn b.) Receive NLP Figure 14.16 Link Pulse Timing Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet CLK DATA CLK DATA CLK CLK DATA TPO± t 48 t 49 t 50 t 51 a.) Transmit FLP and Transmit FLP Burst CLK DATA CLK DATA TPI± 31.25 t 52 62.5 93.75 125 156.25 t 53 t 54 t 55 t 56 b.) Receive FLP TPI± t 59 t 57 t 58 LEDn c.) Receive FLP Burst Figure 14.17 FLP Link Pulse Timing SMSC LAN91C111 REV C 125 DATASHEET Revision 1.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 15 Package Outlines Figure 15.1 128 Pin TQFP Package Outline, 14X14X1.0 Body Table 15.1 128 Pin TQFP Package Parameters A A1 A2 D D/2 D1 E E/2 E1 H L L1 e q W R1 R2 ccc ccc MIN NOMINAL MAX REMARK ~ 0.05 0.95 15.80 7.90 13.80 15.80 7.90 13.80 0.09 0.45 ~ 0.40 Basic 0o 0.13 0.08 0.08 ~ ~ ~ ~ 1.00 16.00 8.00 14.00 16.00 8.00 14.00 ~ 0.60 1.00 1.20 0.15 1.05 16.20 8.10 14.20 16.20 8.10 14.20 0.20 0.75 ~ ~ 0.18 ~ ~ ~ ~ 7o 0.23 ~ 0.20 0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Figure 15.2 128 Pin QFP Package Outline, 3.9 MM Footprint Table 15.2 128 Pin QFP Package Parameters A A1 A2 D D/2 D1 E E/2 E1 H L L1 e q W R1 R2 ccc ccc MIN NOMINAL MAX REMARKS ~ 0.05 2.55 23.70 11.85 19.90 17.70 8.85 13.90 ~ 0.73 ~ 0.5 Basic 0o 0.10 0.13 0.13 ~ ~ ~ ~ ~ 23.90 11.95 20.0 17.90 8.95 14.00 ~ 0.88 1.95 3.4 0.5 3.05 24.10 12.05 20.10 18.10 9.05 14.10 ~ 1.03 ~ ~ ~ ~ ~ ~ ~ 7o 0.30 ~ 0.30 0.0762 0.
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10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Chapter 16 Revision History Table 16.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION Rev. 1.9 (07-17-08) All Updated document references to Rev. C. Rev. 1.9 (07-17-08) Section 13.1, "Maximum Guaranteed Ratings*," on page 105 Fixed commercial temp range to state “0°C to +70°C for LAN91C111” Rev. 1.9 (07-17-08) Cover Added bullet: “Commercial Temperature Range from 0°C to 70°C (LAN91C111)” Rev. 1.