- Standard Microsystems Ethernet Single Chip Product Manual

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.91 (08-18-08) 80 SMSC LAN91C111 REV C
DATASHEET
9.8 Register 18. Status Output - Structure and Bit Definition
0 = No Multiple
Register Access
0 = No
Multiple
Register
Access
INTMDIO: Interrupt
Scheme Select
1 = Interrupt
Signaled With
MDIO Pulse
During Idle
1 = Interrupt
Signaled
With MDIO
Pulse During
Idle
0 = Interrupt
Not Signaled
On MDIO
0 = Interrupt
Not Signaled
On MDIO
Reserved: Reserved for
Factory Use
INT LNKFAIL LOSSSYNC CWRD SSD ESD RPOL JAB
R R/LT R/LT R/LT R/LT R/LT R/LT R/LT
00 0 000 0 0
SPDDET DPLXDET Reserved Reserved Reserved Reserved Reserved Reserved
R/LT R/LT R R R R R R
10 0 00000
INT: Interrupt Detect 1 = Interrupt Bit(s)
Have Changed
Since Last Read
Operation.
0 = No Change
LNKFAIL: Link Fail Detect 1 = Link Not
Detected
0 = Normal
LOSSSYNC: Descrambler Loss of 1 = Descrambler
Has Lost
Synchronization
Synchronization
Detect
0 = Normal
CWRD: Codeword Error 1 = Invalid 4B5B
Code Detected On
Receive Data
0 = Normal