- Standard Microsystems Ethernet Single Chip Product Manual

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C 53 Revision 1.91 (08-18-08)
DATASHEET
LS2A, LS1A, LS0A – LED select Signal Enable. These bits define what LED control signals are routed
to the LEDA output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected.
LS2B, LS1B, LS0B – LED select Signal Enable. These bits define what LED control signals are routed
to the LEDB output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected.
10 Full Duplex 0 0 0 1 X X 1
0101XX 1
10XX01 1
10 Half Duplex 0 0 0 0 X X 0
0100XX 0
10XX00 0
LS2A LS1A LS0A LED SELECT SIGNAL – LEDA
0 0 0 nPLED3+ nPLED0 – Logical OR of 100Mbps Link detected 10Mbps Link detected
(default)
0 0 1 Reserved
0 1 0 nPLED0 - 10Mbps Link detected
0 1 1 nPLED1 - Full Duplex Mode enabled
1 0 0 nPLED2 - Transmit or Receive packet occurred
1 0 1 nPLED3 - 100Mbps Link detected
1 1 0 nPLED4 - Receive packet occurred
1 1 1 nPLED5 - Transmit packet occurred
LS2B LS1B LS0B LED SELECT SIGNAL – LEDB
0 0 0 nPLED3+ nPLED0 – Logical OR of 100Mbps Link detected 10Mbps Link detected
(default)
0 0 1 Reserved
0 1 0 nPLED0 - 10Mbps Link detected
0 1 1 nPLED1 – Full Duplex Mode enabled
1 0 0 nPLED2 – Transmit or Receive packet occurred
1 0 1 nPLED3 - 100Mbps Link detected
1 1 0 nPLED4 - Receive packet occurred
1 1 1 nPLED5 - Transmit packet occurred
WHAT DO YOU
WANT TO DO?
AUTO-NEGOTIATION
CONTROL BITS
SPEED AND DUPLEX MODE CONTROL
FOR THE PHY
DUPLEX
MODE
CONTROL
FOR THE
MAC