- Standard Microsystems Ethernet Single Chip Product Manual

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C 123 Revision 1.91 (08-18-08)
DATASHEET
Table 14.4 Link Pulse Timing Characteristics
SYM PARAMETER
LIMIT UNIT CONDITIONS
MIN TYP MAX
t42 NLP Transmit Link Pulse Width See Figure 7.8 nS
t43 NLP Transmit Link Pulse Period 8 24 mS
t44 NLP Receive Link Pulse Width Required
For Detection
50 nS
t45 NLP Receive Link Pulse Minimum Period
Required For Detection
6 7 mS link_test_min
t46 NLP Receive Link Pulse Maximum
Period Required For Detection
50 150 mS link_test_max
t47 NLP Receive Link Pulse Required To
Exit Link Fail State
333Link
Pulses
lc_max
t48 FLP Transmit Link Pulse Width 100 150 nS
t49 FLP Transmit Clock Pulse to Data Pulse
Period
55.5 62.5 69.5 μS interval_timer
t50 FLP Transmit Clock Pulse to Clock Pulse
Period
111 125 139 μS
t51 FLP Transmit Link Pulse Burst Period 8 22 mS transmit_link_burst_time
r
t52 FLP Receive Link Pulse Width Required
For Detection
50 nS
t53 FLP Receive Link Pulse Minimum Period
Required For Clock Pulse Detection
525μS flp_test_min_timer
t54 FLP Receive Link Pulse Maximum
Period Required For Clock Pulse
Detection
165 185 μS flp_test_max_timer
t55 FLP Receive Link Pulse Minimum Period
Required For Data Pulse Detection
15 47 μS data_detect_min_timer
t56 FLP Receive Link Pulse Maximum
Period Required For Data Pulse
Detection
78 100 μS data_detect_max_timer
t57 FLP Receive Link Pulse Burst Minimum
Period Required For Detection
5 7 mS nlp_test_min_timer
t58 FLP Receive Link Pulse Burst Maximum
Period Required For Detection
50 150 mS nlp_test_max_timer
t59 FLP Receive Link Pulses Bursts
Required To Detect AutoNegotiation
Capability
333Link
Pulses