28
FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH
BUS INTERFACE
ARBITER
MMU
BUFFER RAM
CSMA/CD
ENDEC
TWISTED PAIR
TRANSCEIVER
AUI
10BASET
DATA BUS
ADDRESS
BUS
CONTROL
EEPROM
EEPROM
WRITE
DATA
REG.
READ
DATA
REG.
TX
FIFO
TX
COMPL
FIFO
RX
FIFO
DMA
INTERFACE
ADDRESSDATA
