SMC91C95 PRELIMINARY ISA/PCMCIA Full Duplex Single-Chip Ethernet and Modem Controller with RAM FEATURES • • • • • • • • • • • • • ISA/PCMCIA Single Chip Ethernet Controller With Modem Support 6 Kbytes Built-In RAM Supports IEEE 802.
TABLE OF CONTENTS FEATURES.......................................................................................................................................................1 PIN CONFIGURATION ....................................................................................................................................3 GENERAL DESCRIPTION...............................................................................................................................4 OVERVIEW ........................
• Network Interface • • Uses Certified SMC9000 Drivers Which Operate with Every Major Network Operating System Software Driver Compatible with SMC91C92, SMC91C94 and SMC91C100 (100 Mbps) Controllers in ISA Mode Software Driver Utilizes Full Capability of 32 Bit Microprocessor PIN CONFIGURATION NC AVSS COLN COLP RECN RECP TPERXN TPERXP AVDD AVSS RBIAS AVDD nXENDEC nEN16 PWRDWN/TXCLK nROM/nPCMCIA VSS ENEEP EESK EECS EEDO/SDOUT EEDI IOS2 IOS1 VDD IOS0 XTAL2 XTAL1 WAKEUP nWAKEUP_EN RESET NC • • AVDD TXP/
GENERAL DESCRIPTION accessed with 40ns access times to any of its registers, including its packet memory. No DMA services are used by the SMC91C95; virtually decoupling network traffic from local or system bus utilization. For packet memory management, the SMC91C95 integrates a unique hardware Memory Management Unit (MMU) with enhanced performance and decreased software overhead when compared to ring buffer and linked list architectures.
read directly by the host. parallel EEPROM can be applications, if needed. receive are fully independent. It has 6 kbytes of internal memory and the MMU manages memory in 256 byte pages. The memory size accommodates the increase in interrupt latency resulting from simultaneous LAN and modem operation as well as the potential for simultaneous transmit and receive traffice in some full duplex applications. The remaining used for XIP The SMC91C95 integrates most of the 802.
Resource allocation: Memory dynamically allocated for transmit and receive Can automatically release memory on successful transmission Fast block move operation for load/unload: CPU sees packet bytes as if stored contiguously Handles 16 bit transfers regardless of address alignment Access to packet through fixed window Fast bus interface: Compatible with ISA type and faster buses Configuration: ISA: Uses non-volatile jumperless setup via serial EEPROM Flexibility: Flexible packet and header processing: C
PIN REQUIREMENTS FUNCTION SYSTEM ADDRESS BUS SYSTEM DATA BUS SYSTEM CONTROL BUS MODEM INTERFACE SERIAL EEPROM ISA PCMCIA NUMBER OF PINS A0-A15 A16 A17 A18 A19 AEN A0-A15 nFWE nFCS 21 D0-D15 D0-D15 16 RESET BALE nIORD nIOWR nMEMR IOCHRDY nIOCS16 nSBHE INTR0 INTR1 INTR2 INTR3 RESET nWE nIORD nIOWR nOE nWAIT nIOIS16 nCE2 nIREQ nINPACK nSTSCHG 12 nMRESET MINT nMCS MRDY nMPWDN MIDLEN1 MRINGIN nMRINGOA MRINGOB SPKRIN SPKROUT nMPDOUT MFBK1 nMIS16 nMRESET MINT nMCS MRDY nMPWDN MIDLEN1 MRINGIN nMRIN
FUNCTION ISA PCMCIA NUMBER OF PINS CRYSTAL OSC. XTAL1 XTAL2 XTAL1 XTAL2 2 POWER VDD AVDD VDD AVDD 12 GROUND GND AGND GND AGND 12 TPERXP TPERXN TPETXP TPETXN TPETXDP TPETXDN TPERXP TPERXN TPETXP TPETXN TPETXDP TPETXDN 6 RECP RECN COLP COLN TXP/nCOLL TXN/nCRS RECP RECN COLP COLN TXP/nCOLL TXN/nCRS 6 LEDs nLNKLED/TXD nRXLED/RXCLK nBSELED/RXD nTXLED/nTXEN nLNKLED/TXD nRXLED/RXCLK nBSELED/RXD nTXLED/nTXEN 4 MISC.
DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME 113 SYMBOL TYPE DESCRIPTION nROM/ nPCMCIA I/O4 with pullup This pin is sampled at the end of RESET. When this pin is sampled low the SMC91C95 is configured for PCMCIA operation and all pin definitions correspond to the PCMCIA mode. For ISA operation this pin is left open and is used as a ROM chip select output that goes active when nMEMR is low and the address bus contains a valid ROM address.
DESCRIPTION OF PIN FUNCTIONS PIN NO. 81 NAME nByte High Enable nCard Enable 2 83 SYMBOL TYPE DESCRIPTION nSBHE I with pullup ISA - Byte High Enable input. Asserted (low) by the system to indicate a data transfer on the upper data byte. nCE2 PCMCIA - Card Enable 2 input. Used to select card on odd byte accesses. Ready IOCHRDY nWait nWAIT Data Bus D0-D15 I/O24 Bidirectional. 16 bit data bus used to access the SMC91C95 internal registers. The data bus has weak internal pullups.
DESCRIPTION OF PIN FUNCTIONS PIN NO. 91 NAME SYMBOL nInterrupt Request nIREQ Interrupt 1 INTR1 TYPE PCMCIA - Active low interrupt request output. Pin acts as a Ready pin during power-up. The pin should be pulled low within 10us of the application of the VCC or Reset (which ever occurs later). It remains low(0) until the CIS is loaded in the Internal SRAM. The high(1) state indicates to the host controller that the device is ready. O24 nINPACK 92 DESCRIPTION ISA - Output.
DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL TYPE nIOIS16 DESCRIPTION PCMCIA - Active low output asserted whenever the SMC91C95 is in 16 bit mode, and “Enable Function” bit in the ECOR register is high, nREG is low and A4-A15 decode to the LAN address specified in I/O Base Registers 0 and 1 in PCMCIA attribute space. 88 nI/O Read nIORD IS with pullup Input. Active low read strobe used to access the SMC91C95 IO space. 87 nI/O Write nIOWR IS with pullup Input.
DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME 26 SYMBOL TYPE DESCRIPTION MIDLEN1 O4 Powerdown output to modem controller. This pin is active (high) when either the PWRDWN bit (CSR bit 2) is set or the modem is disabled (not configured). 20 Modem Ring Input MRINGIN I Ring input from the modem controller. Toggles when ringing, low when not ringing. 21 nModem Ring Output A nMRINGOA O4 Ring output signal.
DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL TYPE DESCRIPTION nMIS16 I with pullup Input. When low, it indicates a 16 bit modem, otherwise the modem is 8 bit wide. Used to determine if nIOIS16 (PCMCIA) and nIOCS16 (ISA) need to be asserted for modem cycles. The value of this pin may change from cycle to cycle. 16 n16 Bit Modem 110 EEPROM Clock EESK O4 Output. 4µs clock used to shift data in and out of the serial EEPROM. 109 EEPROM Chip Select EECS O4 Output. Serial EEPROM chip select.
DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL TYPE nReceive LED nRXLED OD16 Internal ENDEC - Receive LED output. Receive Clock RXCLK I with pullup External ENDEC - Receive clock input. nLNKLED OD16 Internal ENDEC - Link LED output. Transmit Data TXD 0162 External ENDEC - Transmit Data output. 111 Enable EEPROM ENEEP I with pullup Input. This active high input enables the EEPROM to be read or written by the SMC91C95. Internally pulled up.
DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL TYPE DESCRIPTION 125 AUI Collision COLP COLN Diff. Input AUI collision differential inputs. A collision is indicated by a 10 MHz signal at this input pair. TPE Receive TPERXP TPERXN Diff. Input 10BASE-T receive differential inputs. TPE Transmit TPETXP TPETXN Diff. Output Internal ENDEC differential outputs. TPE Transmit Delayed TPETXDP TPETXDN Diff. Output 10BASE-T delayed transmit differential outputs.
DESCRIPTION OF PIN FUNCTIONS PIN NO. 116 NAME SYMBOL TYPE DESCRIPTION nExternal ENDEC nXENDEC I with pullup When tied low the SMC91C95 is configured for external ENDEC. When tied high or left open the SMC91C95 will use its internal encoder/decoder.
nIRQ BUFFER SYSTEM BUS 3 18 PROM DATA ADDRESS N/C XTAL1 A0-19 D0-15 XTAL2 EEDI IOS0 IOS1 IOS2 nEN16 ENEEP SMC91C95 4 INTR0-3 EESK EEDO 4 IOCHRDY EECS nROM nIOCS16 nMEMR nIORD, nIOWR, nSBHE RESET BALE AEN 20 MHz EEPROM SERIAL TPETXN TPETXP RBIAS COLN COLP RECN RECP TXN TXP TPERXN TPERXP TPETXDN TPETXDP 4 LEDs DIAGNOSTIC 10BASET AUI CABLE SIDE Figure 1 - SMC91C95 System Block Diagram for ISA Bus with Boot PROM
PCMCIA CONNECTOR nCE1 nCE2 nREG nWE 10BASE-T/AUI INTERFACE A0-A9, A15 nIORD nIOWR SPKROUT STSCHG nMRESET RESET MINT nIREQ D0-D15 nMCS SMC91C95 MRDY nRESET nCS RDY nIOIS16 nINPACK nWAIT nOE MPWDN PWDN MRINGIN RINGIN MRINGOB nFWE SPKRIN PHONE LINE INT MODEM CHIPSET RINGOUTB SPKR nFCS nWE nCE CS,SK,DI,DO nOE EXTENDED ATTRIBUTE D0-D7 EPROM 2816 A0-X (Optional) SERIAL EPROM (ISA-Hy9346) (PCMCIA-Hy93c66) Figure 2 - SMC91C95 System Block Diagram for Dual Function PCMCIA Card 19
MODEM INTERFACE DATA BUS ADDRESS BUS MANAGEMENT ARBITER ENDEC CSMA/CD AUI BUS INTERFACE CONTROL MMU TWISTED PAIR TRANSCEIVER RAM Figure 3 - SMC91C95 Internal Block Diagram 20 10BASE-T
FUNCTIONAL DESCRIPTION The Ethernet controller function includes a built-in 6kbyte RAM for packet storage. This RAM buffer is accessed by the CPU through two sequential access regions of 3 kbytes each. The RAM access is internally arbitrated by the SMC91C95 and dynamically allocated between transmit and receive packets using 256 byte pages. The Ethernet controller functionality is identical to the SMC91C94 except where indicated otherwise.
Table 2 - Bus Transactions in PCMCIA Mode A0 nCE1 nCE2 D0-D7 D8-D15 0 0 X even byte - 1 0 X odd byte - X 1 X 16 BIT MODE 0 0 0 even byte odd byte otherwise 0 0 1 even byte - 1 0 1 odd byte X 1 0 - X 1 1 8 BIT MODE ((IOis8=1) + (nEN16=1).
Table 3 - SMC91C95 Address Spaces SIGNALS USED ISA PCMCI A ON-CHIP PCMCIA Attribute Memory nOE nWE N Y N (external ROM) PCMCIA Configuration Registers nOE nWE N Y Modem I/O Space nIORD nIOWR Y Ethernet I/O Space (1) nIORD nIOWR Y DEPTH WIDTH Up to 32k locations, only even bytes are usable 8 bits on even addresses Y 64 locations, only even bytes are usable 8 bits Y N 8 locations 8 bit Y Y 16 locations 8 or 16 bits (1) This space also allows access to the PCMCIA Configuration
The TX area is seen by the CPU as a window through which packets can be loaded into memory before queuing them in the TX FIFO of packets. The TX area can also be used to examine the transmit completion status after packet transmission. The internal DMA interface can arbitrate for RAM access and request memory from the MMU when necessary. An encoder/decoder block interfaces the CSMA/CD block on the serial side.
PHYSICAL MEMORY RCV BIT POINTER REGISTER TX PACKET NUMBER 11-BIT LOGICAL ADDRESS RCV VS. TX AREA SELECTION PAGE = 256 bytes 2K TX AREA MMU RX PACKET NUMBER 2K RX AREA MMU FIGURE 4 - MAPPING AND PAGING VS.
PACKET NUMBER REGISTER STATUS MEMORY COUNT PACKET #A CPU SIDE DATA B STATUS A TX FIFO COUNT DATA PACKET #B C TO CSMA B STATUS TX COMPLETION FIFO COUNT PACKET #C C DATA FIFO PORTS REGISTER LINEAR ADDRESS MMU MAPPING FIGURE 5 - TRANSMIT QUEUES AND MAPPING 26
MEMORY FIFO PORTS REGISTER STATUS D COUNT PACKET #D DATA E CPU SIDE RX FIFO STATUS D COUNT PACKET #E DATA E FROM CSMA LINEAR ADDRESS MMU MAPPING FIGURE 6 - RECEIVE QUEUE AND MAPPING 27
FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH 28 CONTROL ADDRESS BUS DATA BUS WRITE DATA REG. READ DATA REG.
word is used to specify the total number of bytes, and that in turn is followed by the data area. The data area holds the packet itself, and its length is determined by the byte count. The packet memory format is word oriented. PACKET FORMAT IN BUFFER MEMORY The packet format in memory is similar for the TRANSMIT and RECEIVE areas.
The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS, followed by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The SMC91C95 does not insert its own source address. On receive, all bytes are provided by the CSMA side. BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE.
RECEIVE FRAME STATUS WORD This word is written at the beginning of each receive frame in memory. It is not available as a register. HIGH BYTE ALGN ERR BROD CAST BAD CRC LOW BYTE ODD FRM TOOLN G TOO SHORT HASH VALUE 5 4 3 2 ALGNERR - Frame had alignment error. MULT CAST 1 0 HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by receive routines to speed up the group address search.
structure is similar for ISA and PCMCIA modes with the following exceptions: INTERRUPT STRUCTURE The SMC91C95 merges two main interrupt sources into a single interrupt line. One source is the Ethernet interrupt and the other is the modem interrupt. The Ethernet interrupt is conceptually equivalent to the SMC91C92 interrupt line; it is the OR function of all enabled interrupts within the Ethernet core. The modem interrupt is an input pin (MINT).
RESET LOGIC POR - The pins and bits involved in the different reset mechanisms are: nMRESET SRESET MCOR, RESET - Input Pin SOFT RST - Internal circuit activated by Power On Output pin to reset modem Soft Reset bit in ECOR and one SRESET bit for each function. EPH Soft Reset bit in RCR Table 5 - Reset Functions RESETS THE FOLLOWING FUNCTIONS ACTIVATES SAMPLES ISA VS.
POWERDOWN LOGIC SMC91C95 Powerdown States: The pins and bits involved in powerdown are: A) The SMC91C95 is Off and no Clock is running B1) The SMC91C95 of Off with clock running (No Active LAN or Host Data Transfer) TBD Current Reduction with No Link Pulses for LAN access B2) The SMC91C95 of Off with clock running (No Active LAN or Host Data Transfer) TBD Current Reduction with Link active C) The SMC91C95 is completely powered up (With Active LAN or Host Data transfer) 80MA Max, 40MA typ. 1. 2. 3. 4. 5.
Table 6 - Powerdown Functions POWERDOWN ENTERED POWERDOWN EXITED POWERS DOWN: DOES NOT POWER DOWN (B2) Power State nWAKEUP (Pin) When pin is low and reset is inactive When pin goes high Ethernet Function (Link logic enabled) Modem Function, Attribute memory and PCMCIA configuration Registers access, Link Logic (B2) Power State PWRDN bit in Control Register When bit is set Write access to I/O space or reset Ethernet Function.
SMC91C95 need not be used (if serial EEPROM is being used). Internal to the SMC91C95, the memory addressing logic will allow byte or word on odd byte address access (A0=1), the SMC91C95 will generate an arbitrary value of zero (0) since the PCMCIA specification states that the high byte of a word access in attribute memory is a don’t care. This allows backward compatibility to 8 bit hosts. Internal VS External Attribute Memory Map The Internal VS External EPROM attribute memory decodes are shown below.
I/O SPACE (ISA and PCMCIA Mode) In ISA mode, the base I/O space is determined by the IOS0-IOS2 inputs and the EEPROM contents. A4-A15 are compared against the base I/O address for I/O space accesses. To limit the I/O space requirements to 16 locations, the registers are assigned to different banks. The last word of the I/O area is shared by all banks and can be used to change the bank in use. In PCMCIA mode nREG (along with nIORD or nIOWR) defines an I/O access regardless of the A4-A15 value.
Table 9 - Internal I/O Space Mapping BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 0 TCR CONFIG MMU COMMAND MT0-MT1 ECOR (low byte) ECSR (high byte) MCOR (low byte) MCSR (high byte) 2 EPH STATUS BASE PNR ARR MT2-MT3 4 RCR IA0-IA1 FIFO PORTS MT4-MT5 EBASE0 (high byte) IOEIR (low byte) MBASE0 (high byte) 6 COUNTER IA2-IA3 POINTER MT6-MT7 EBASE1 (low byte) MBASE1 (low byte) 8 MIR IA4-IA5 DATA MGMT A MCR GENERAL PURPOSE DATA REVISION C RESERVED (0) CONTROL INTERRUPT ERCV E
BANK SELECT REGISTER OFFSET E HIGH BYTE NAME BANK SELECT REGISTER TYPE READ/WRITE SYMBOL BSR 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BS2 BS1 BS0 0 0 0 LOW BYTE X X X X X BS2, BS1, BS0 - Determine the bank presently in use. The BANK SELECT REGISTER is always accessible regardless of the value of BS0-BS2. The BANK SELECT REGISTER is always accessible except in PCMCIA powerdown mode and is used to select the register bank in use.
I/O SPACE - BANK0 OFFSET 0 NAME TRANSMIT CONTROL REGISTER TYPE READ/WRITE SYMBOL TCR This register holds bits programmed by the CPU to control some of the protocol transmit options. HIGH BYTE FDSE 0 LOW BYTE X EPH LOOP STP SQET 0 0 FDUPL X 0 PAD_E N 0 X X X X MON_ CSN NOCRC 0 X 0 FORCO L LOOP TXENA 0 0 0 FDSE - Full Duplex Switched Ethernet. When set, the SMC91C95 is configured for Full Duplex Switched Ethernet, it defaults clear to normal CSMA/CD protocol.
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared, the SMC91C95 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. LOOP - Local Loopback. When set, transmit frames are internally looped to the receiver after the encoder/decoder. Collision and Carrier Sense are ignored. No data is sent out. Defaults low to normal mode.
I/O SPACE - BANK0 OFFSET 2 NAME EPH STATUS REGISTER TYPE READ ONLY SYMBOL EPHSR This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use the copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used for real time values (like TXENA and LINK OK).
TXENA bit in TCR is reset. Cleared when TXENA is set high. detection for magic packet - enabled by nWAKEUPEN pin (92 QFP) or WAKEUP_EN in CTR. LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit frame. NOTE: If the MP mode is activated using the nWAKEUPEN pin, the pin must be deasserted to exit the mode. MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced.
I/O SPACE - BANK0 OFFSET 4 HIGH BYTE NAME RECEIVE CONTROL REGISTER TYPE READ/WRITE SYMBOL RCR SOFT_ RST FILT_ CAR 0 0 0 0 STRIP_ CRC RXEN 0 0 0 0 0 0 0 0 ALMUL PRMS RX_ ABORT 0 0 0 LOW BYTE 0 0 0 0 0 RXEN - Enables the receiver when set. If cleared, completes receiving current frame and then goes idle. Defaults low on reset. SOFT_RST - Software activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low.
I/O SPACE - BANK0 OFFSET 6 NAME COUNTER REGISTER TYPE READ ONLY SYMBOL ECR Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared when reading the register and do not wrap around beyond 15. HIGH BYTE NUMBER OF EXC.
I/O SPACE - BANK0 OFFSET 8 NAME MEMORY INFORMATION REGISTER HIGH BYTE TYPE READ ONLY SYMBOL MIR FREE MEMORY AVAILABLE (IN BYTES * 256 * M) 0 0 LOW BYTE 0 1 1 0 0 0 0 0 MEMORY SIZE (IN BYTES *256 * M) 0 0 0 1 1 0 MEMORY SIZE - This register can be read to determine the total memory size, and will always read 18H (6144 bytes) for the SMC91C95. FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory.
I/O SPACE - BANK0 OFFSET A NAME MEMORY CONFIGURATION REGISTER TYPE Lower Byte READ/WRITE Upper Byte READ ONLY HIGH BYTE SYMBOL MCR MEMORY SIZE MULTIPLIER 0 LOW BYTE 0 1 1 0 0 1 1 MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M) 0 0 0 0 0 0 0 0 The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY CURRENTLY IN USE.
I/O SPACE - BANK1 OFFSET 0 NAME CONFIGURATION REGISTER TYPE READ/WRITE SYMBOL CR The Configuration Register holds bits that define the device configuration and are not expected to change during run-time. This register is part of the EEPROM saved setup in ISA mode only. In PCMCIA mode, this register is initialized to the state as defined below the corresponding bits as if no EEPROM was present in ISA mode (i.e. ENEEP pin is a don’t care in PCMCIA mode).
INT SEL1 INT SEL0 INTERRUPT PIN USED 0 0 1 1 0 1 0 1 INTR0 INTR1 INTR2 INTR3 49
I/O SPACE - BANK1 OFFSET 2 NAME BASE ADDRESS REGISTER TYPE READ/WRITE SYMBOL BAR For ISA mode only, this register holds the I/O address decode option chosen for the I/O and ROM space. It is part of the EEPROM saved setup, and is not usually modified during run-time. NOTE: This register should ONLY be used in ISA mode. In PCMCIA mode, this register is read only.
I/O SPACE - BANK1 OFFSET 4 THROUGH 9 NAME INDIVIDUAL ADDRESS REGISTERS TYPE READ/WRITE SYMBOL IAR These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload in ISA mode only. The registers can be modified by the software driver, but a STORE operation will not modify (in ISA mode only) the EEPROM Individual Address contents. The SMC91C95 in PCMCIA mode knows nothing about the location or structure of the IEEE Ethernet Address stored in the EEPROM.
I/O SPACE - BANK1 OFFSET A NAME GENERAL PURPOSE REGISTER HIGH BYTE TYPE READ/WRITE SYMBOL GPR HIGH DATA BYTE 0 0 0 LOW BYTE 0 0 0 0 0 0 0 0 LOW DATA BYTE 0 0 0 0 0 EEPROM, that is normally accidental Store operations. This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be used by the software driver.
I/O SPACE - BANK1 OFFSET C HIGH BYTE LOW BYTE NAME CONTROL REGISTER 0 RCV_ BAD 0 0 0 LE ENABLE CR ENABLE TE ENABLE 0 0 0 TYPE READ/WRITE PWRDWN WAKEU P_EN 0 AUTO RELEASE 0 1 X EEPROM SELECT X SYMBOL CTR X 0 X 1 RELOAD STORE 0 0 AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful (when TX_SUC is set).
contents in the SMC91C95 CIS SRAM as defined in Table 10. CR ENABLE - Counter Roll over Enable. When set it enables the CTR_ROL bit as one of the interrupts merged into the EPH INT bit. Defaults low (disabled). STORE In ISA Mode: The STORE bit when set, stores the contents of all relevant registers in the serial EEPROM. This bit is cleard upon completing the operation. TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged into the EPH INT bit.
Table 10 - PCMCIA EEPROM to SRAM Memory Map ATTRIBUTE MEMORY ATTRIBUTE EEPROM ADDRESS SMC91C95 SRAM HOST ADDRESS (HEX) DATA IN WORDS IN BYTES 000 Data byte 0 Word 1 - Low Byte Byte 0 001 Don’t Care 002 Data byte 1 Word 1 - High Byte Byte1 003 Don’t Care 004 Data byte 2 Word 2 - Low Byte Byte2 005 Don’t Care 006 Data byte 3 Word 2 - High Byte Byte3 .. .. .. ..
I/O SPACE - BANK2 OFFSET 0 NAME MMU COMMAND REGISTER TYPE WRITE ONLY BUSY Bit Readable SYMBOL MMUCR This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three command bits determine the command issued as described below: HIGH BYTE LOW BYTE COMMAND x y 0 0 N2 N1 N0/BUS Y z 0 COMMAND SET: xyz 000 0) NOOP - NO OPERATION 001 1) ALLOCATE MEMORY FOR TX - N2,N1,N0 defines the amount of memory requested as (value + 1) * 256 bytes.
110 6) ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. 111 7) RESET TX FIFOs - This command will reset both TX FIFOs: the TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO. This command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue.
I/O SPACE - BANK2 OFFSET 2 NAME PACKET NUMBER REGISTER TYPE READ/WRITE SYMBOL PNR PACKET NUMBER AT TX AREA 0 0 0 0 0 PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this OFFSET 3 0 0 0 register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command.
I/O SPACE - BANK2 OFFSET 4 NAME FIFO PORTS REGISTER TYPE READ ONLY SYMBOL FIFO This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from this register. HIGH BYTE REMPT Y 1 LOW BYTE RX FIFO PACKET NUMBER 0 0 0 TEMPT Y 1 0 0 0 0 TX DONE PACKET NUMBER 0 0 0 REMPTY - No receive packets queued in the RX FIFO.
I/O SPACE - BANK2 OFFSET 6 HIGH BYTE NAME POINTER REGISTER TYPE READ/WRITE RCV AUTO INCR. READ ETEN 0 0 0 0 0 0 LOW BYTE SYMBOL PTR POINTER HIGH 0 0 0 0 0 0 POINTER LOW 0 0 0 0 0 POINTER REGISTER -The value of this register determines the address to be accessed within the transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set. The increment is by one for every byte access, and by two for every word access.
I/O SPACE - BANK2 OFFSET 8 THROUGH Ah NAME DATA REGISTER TYPE READ/WRITE SYMBOL DATA DATA HIGH DATA LOW DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register. order to and from the FIFO is preserved. Byte and word accesses can be mixed on the fly in any order. This register is mapped into two uni-directional FIFOs that allow moving words to and from the SMC91C95 regardless of whether the pointer address is even or odd.
I/O SPACE - BANK2 OFFSET C X OFFSET C NAME INTERRUPT STATUS REGISTER X SYMBOL IST ERCV INT EPH INT RX_OVR N INT ALLOC INT TX EMPTY INT TX INT RCV INT 0 0 0 0 1 0 0 NAME INTERRUPT ACKNOWLEDGE REGISTER TYPE WRITE ONLY RX_OVR N INT ERCV INT OFFSET D TYPE READ ONLY TX EMPTY INT NAME INTERRUPT MASK REGISTER SYMBOL ACK TX INT TYPE READ/WRITE SYMBOL MSK ERCV INT EPH INT RX_OVR N INT ALLOC INT TX EMPTY INT TX INT RCV INT 0 0 0 0 0 0 0 This register can be read and writte
WAKE_UP - “Magic Packet” is received if enabled RX_OVRN INT - Set when the receiver overruns due to a failed memory allocation. The RX_OVRN bit of the EPHSR will also be set, but if a new packet is received it will be cleared. The RX_OVRN INT bit, however, latches the overrun condition for the purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with the RX_OVRN INT bit set. TX INT - Set when at least one packet transmission was completed.
D4 64 FIGURE 9 - INTERRUPT STRUCTURE FAILED OE BUS nRDIST 5 MERGED INTO EPH INT nQ S Q DATA D 4 3 2 1 16 D0-7 D8-15 REGISTER 4 REGISTER 5 MASK 0 INTERRUPT 1 STATUS 2 INTERRUPT 3 TX COMPLETION FIFO NOT EMPTY EPHSR INTERRUPTS TX_SVC TXENA TEMASK CRMASK CTR-ROL LEMASK ON LINK ERR nQ S Q ALLOCATION D RX_OVRN (EPHSR) EDGE DETECTOR nWRACK D2 TX FIFO EMPTY RCV FIFO nOE 0 NOT EMPTY MAIN INTERRUPTS EPH INT RX_OVRN INT ALLOC INT EMPTY INT TX TX INT RCV INT
I/O SPACE - BANK 3 OFFSET 0 THROUGH 7 NAME MULTICAST TABLE LOW BYTE TYPE READ/WRITE SYMBOL MT MULTICAST TABLE 0 0 0 0 HIGH BYTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MULTICAST TABLE 1 0 0 0 LOW BYTE 0 0 MULTICAST TABLE 2 0 0 0 HIGH BYTE 0 0 MULTICAST TABLE 3 0 0 0 LOW BYTE 0 0 MULTICAST TABLE 4 0 0 0 HIGH BYTE 0 0 MULTICAST TABLE 5 0 0 0 LOW BYTE 0 0 MULTICAST TABLE 6 0 0 0 HIGH BYTE 0 0 MULTICAST TABLE 7 0 0 0 0 The 64
I/O SPACE - BANK3 OFFSET 8 NAME MANAGEMENT INTERFACE TYPE READ/WRITE HIGH BYTE 0 0 1 0 nXNDE C IOS2 IOS1 IOS0 MDOE MCLK MDI MDO 0 0 0 0 1 LOW BYTE 0 SYMBOL MGMT 1 1 nXNDEC - Read only bit reflecting the status of the nXENDEC pin. MDI - Reads the value of the EEDI pin. MDCLK - The value of this bit drives the EESK pin when MDOE=1. IOS0-IOS2 - Read only bits reflecting the status of the IOS0-IOS2 pins.
I/O SPACE - BANK3 OFFSET A NAME REVISION REGISTER TYPE READ ONLY SYMBOL REV HIGH BYTE 0 0 LOW BYTE 1 1 0 0 CHIP 0 1 1 0 0 REV 1 0 0 CHIP - Chip ID. Can be used by software drivers to identify the device used. 0 0 REV - Revision ID. Incremented for each revision of a given device.
I/O SPACE - BANK 3 OFFSET C NAME EARLY RCV REGISTER TYPE READ/WRITE SYMBOL ERCV HIGH BYTE 0 LOW BYTE 0 1 1 0 RCV DISCR D 0 0 1 1 1 1 ERCV THRESHOLD 0 0 1 RCV DISCRD - Set to discard a packet being received. This bit can be used in conjunction with ERCV THRESHOLD and ERCV INT to process a packet header while it is being received and sicard it if the packet is not desired. Setting this bit will only discard packets that are still in the process of being received.
THEORY OF OPERATION processing flexibility. A receive lookahead scheme like ODI or NDIS drivers is supported by copying a small part of the received packet and letting the upper layer provide a pointer for the rest of the data. If the upper layer indicates it does not want a specific part of the packet, a block move operation starting at any particular offset can be done. Out of order receive processing is also supported: if memory for one packet is not yet available, receive packet processing can continue.
2. FDSE (Full Duplex Switched Ethernet). Enabled by FDSE bit in TCR bit. When the SMC91C95 is configured for FDSE, its transmit and receive paths will operate independently and some CSMA/CD functions are disabled such as Carrier Sense. T front end, AUI front end, or External Endec interface. This collision input is observed by the Transmit State Machine while ‘transmitting’ is true, that is during Preamble, Data, Pad, and CRC states.
TYPICAL FLOW OF EVENTS FOR TRANSMIT S/W DRIVER CSMA/CD SIDE 1 ISSUE ALLOCATE MEMORY FOR TX - N BYTES - the MMU attempts to allocate N bytes of RAM. 2 WAIT FOR SUCCESSFUL COMPLETION CODE - Poll until the ALLOC INT bit is set or enable its mask bit and wait for the interrupt. The TX packet number is now at the Allocation Result Register. 3 LOAD TRANSMIT DATA - Copy the TX packet number into the Packet Number Register.
TYPICAL FLOW OF EVENTS FOR RECEIVE S/W DRIVER 1 CSMA/CD SIDE ENABLE RECEPTION - By setting the RXEN bit. 2 A packet is received with matching address. Memory is requested from MMU. A packet number is assigned to it. Additional memory is requested if more pages are needed. 3 The internal DMA logic generates sequential addresses and writes the receive words into memory. The MMU does the sequential to physical address translation. If overrun, packet is dropped and memory is released.
ISR Save Bank Select & Address Ptr Registers Mask 91C94 Interrupts Read Interrupt Register No Yes RX INTR? Yes TX INTR? Call TX INTR or TXEMPTY INTR No Call RXINTR Get Next TX Yes ALLOC INTR? Packet Available for Transmission? No Yes Write Allocated Pkt # into Packet Number Reg. No Call ALLOCATE Write Ad Ptr Reg.
FIGURE 11 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU 74 OPTIONS TWO INTERRUPT INT ALLOC INT TX TX EMPTY INT INT RCV STATUS REGISTER M.S.
RX INTR Write Ad. Ptr. Reg.
TX INTR Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg.
TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) TXEMPTY = X & TXINT = 1 (Transmission Failed) TXEMPTY = 1 & TXINT = 0 (Everything went through successfully) Read Pkt.
DRIVER SEND ALLOCATE Choose Bank Select Register 2 Issue "Allocate Memory" Command to MMU Call ALLOCATE Read Interrupt Status Register Exit Driver Send Yes Allocation Passed? No Read Allocation Result Register Write Allocated Packet into Packet # Register Store Data Buffer Pointer Write Address Pointer Register Clear "Ready for Packet" Flag Copy Part of TX Data Packet into RAM Enable Allocation Interrupt Write Source Address into Proper Location Copy Remaining TX Data Packet into RAM Enque
needs to burst transmissions it can reduce the receive memory allocation. The driver program the parameter as a function of the following variables: MEMORY PARTITIONING Unlike other controllers, the SMC91C95 does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation.
TX INT bit - Set whenever the TX completion FIFO is not empty. the CPU is not provided with the packet numbers that completed successfully. TX EMPTY INT bit - Set whenever the TX FIFO is empty. AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and their memory is released automatically. NOTE: The pointer register is shared by any process accessing the SMC91C95 memory.
Table 11 - Attribute Memory Decodes Using Serial EPROM ATTRIBUTE MEMORYADDRESS EXTERNAL EPROM STORE 0 - 3FEh INTERNAL SRAM STORE (512 BYTES) CONFIGURATION REGISTERS X 400h-7FFEh X 8000h - 803Eh X Table 12 - Attribute Memory Decodes without Serial EPROM ATTRIBUTE MEMORYADDRESS 0 - 7FFEh EXTERNAL EPROM STORE INTERNAL SRAM STORE (512 BYTES) CONFIGURATIO N REGISTERS X 8000h - 803Eh X 81
PCMCIA CONFIGURATION REGISTERS DESCRIPTION Ethernet Function (Base Address 8000h) 8000h - Ethernet Configuration Option Register (ECOR) 7 6 SRESET LevIREQ 0 1 5 0 4 0 3 2 1 0 WRATTRI B Enable IREQ Enable Base and Limit Enable Function 0 0 0 0 board decoder is used to select the function. If cleared, the decoder is disabled and it is assumed that the host provides for the decoding.
8002h - Ethernet Configuration and Status Register (ECSR) 7 6 5 4 3 IOIs8 0 0 0 0 0 2 1 0 Pwrdwn Intr IntrACK 0 0 0 When this bit and Enable IREQ Routing are set, -IREQOut is asserted. BIT 7 - Not defined BIT 6 - Not defined All setting and resetting of this bit is edge triggered with exception of the internally generated reset signal for the modem / Ethernet related PC card registers.
I/O Base Register 0 & 1 (I/O Base 0 & 1) Address 800Ah & 800Ch 800Ah - Ethernet I/O BASE Register 0 7 6 5 4 3 2 1 0 A7 A6 A5 A4 0 0 0 0 0 0 0 0 0 0 0 0 800Ch - Ethernet I/O BASE Register 1 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 0 0 0 0 0 0 1 1 Since only A15 to A4 are decoded by the controller (64K address space), it is up to the host to resolve any conflicts with addressing above 64K. The default decode value is 300h (A9=A8=1, others=0).
Modem Function (Base Address 8020h) 8020h - Modem Configuration Option Register (MCOR) 7 6 SRESET LevIREQ 0 1 5 0 4 3 0 0 BIT 7 - SRESET: This bit when set clears all internal registers associated with the Modem function (except itself) and asserts the nMRESET pin . 2 1 0 Enable IREQ Enable Base and Limit Enable Function 0 0 0 BIT 1 - Enable Base and Limit: This bit enables the on board modem I/O base decoder. If set, the on-board decoder is used to select the function.
8022h - Modem Configuration and Status Register (MCSR) Address 8022h 7 6 5 4 3 2 1 0 Changed SigChg IOIs8 Reserved Audio Pwrdwn Intr IntrACK 0 0 0 0 0 0 0 0 pulse on the output ringing signals as appropriate. The pulse duration is determined by the input signal MRINGIN. MRINGIN is then passed to the outputs. Bit 7 - Changed: This bit is the logical OR of the CREADY/-Bsy and (RINGEVENT bit logically anded with RINGENABLE) states.
8024h - Pin Replacement Register (PRR) 7 6 5 4 3 2 1 Cready/Bsy 0 0 0 Rready/Bsy 0 0 0 1 0 value for Rready/Bsy bit. A CPU write to this bit is successful only if the Rready/-Bsy bit is being written as one(1).
8028h - Extended Status Register(ESR) 7 6 5 4 3 2 1 RINGEVENT 0 0 0 0 0 RINGENABLE 0 0 0 0 host writes a one (1) and the change bit in the MCSR register is unaffected if the host writes a zero (0). RINGEVENT: This bit is latched to a one at the start of each ring frequency cycle (input from ring input from modem, the MRINGIN signal going high). When this bit and RINGENABLE are both set to a one (1), the Changed bit in the MCSR is set to a one(1).
802Ah - Modem I/O BASE Register 0 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 0 0 0 0 0 0 0 0 0 0 0 802Ch - Modem I/O BASE Register 1 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 0 0 0 0 0 0 1 1 Base 0 are always 0. Since only A15 to A4 are decoded by the controller (64K address space), it is up to the host to resolve any conflicts with addressing above 64K.
8032h - Modem I/O Size Register Modem I/O Size Mask 0 0 0 0 0 1 1 1 SMC91C95 will tri-state the data bus during Modem I/O space accesses. In ISA mode, nMCS is disabled (1). No address decodeing for the modem will be done. The I/O Size Register holds a bit mask used to specify the number of address lines decoded by the Modem function. Each bit in the register represents an I/O address line.
FUNCTIONAL DESCRIPTION OF THE BLOCKS can allocate, therefore there is no need for the programmer or the hardware to check FIFO full conditions. MEMORY MANAGEMENT UNIT The MMU interfaces the on-chip RAM on one side and the arbiter on the other for address and data flow purposes. For allocation and deallocation, it interfaces the arbiter only.
A valid comparison does not yet indicate a valid I/O cycle is in progress, as the addresses could be used for a memory cycle, or could even glitch through a valid value. Only when nIORD or nIOWR are activated the I/O cycle begins. The arbiter uses the pointer register as the CPU provided address, and the internal DMA address from the CSMA/CD side as the addresses to be provided to the MMU.
• write cycle starts and there is more than two bytes in the write FIFO. • The cycle time is defined as the time between leading edges of read from the Data Register, or equivalently between trailing edges of write to the Data Register. For example, in an ISA system the cycle time of a 16 bit transfer will be at least 2 clocks for the I/O access to the SMC91C95 + one clock for the memory cycle) = 3 clocks. In absolute time it means 375ns for a 8MHz bus, and 240ns for a 12.5 MHz bus.
the Fifo Ports Register. The CPU can remove a packet number from this FIFO by issuing a TX INT acknowledge. The CPU can determine if this FIFO is empty by reading the TX INT bit or the FIFO Ports Register. Packets with bad CRC can be received if the RCV_BAD bit in the configuration register is set.
FIGURE 16 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS 95 MMU DECODER RESULT REGISTER ALLOCATION REGISTER COMMAND PACK # OUT RELEASE ALLOCATE CPU ADDRESS PACKET NUMBER TX DONE LOGICAL ADDRESS PACKET # RAM PACK # OUT PHYSICAL ADDRESS MMU RELEASE ALLOCATE CSMA ADDRESS NUMBER RX FIFO RX PACKET RD FIFO WR RX FIFO DMA PACKET NUMBER TX COMPLETION TX FIFO REGISTER PACKET NUMBER CSMA/CD
Note that the receive status word of any packet is available only through memory and is not readable through any other register. In order to let the CPU know about receive overruns, the RX_OVRN bit is latched into the Interrupt Status Register, which is readable by the CPU at any time. CSMA BLOCK The CSMA/CD block is first interfaced via its control registers in order to define its operational configuration.
transmission, data is automatically looped back to the receiver except during collision periods, in which case the input to the receiver is network data. During collisions, should the receive input go idle prior to the transmitter going idle, input to the receiver switches back to the transmitter within 9 bit times. Following transmission, the transmitter performs a SQE test. This test exercises the collision detection circuitry within the 10BASE-T interface.
can be divided into transmit and receive functions. function is transceiver. performed by the external Transmit Functions Receive Functions Manchester Encoding Receive Drivers The PHY encodes the transmit data received from the MAC. The encoded data is directed internally to the selected output driver for transmission over the twisted-pair network or the AUI cable. Data transmission and encoding is initiated by the Transmit Enable input, TXE, going low.
transceiver sends a 10MHz signal to the PHY upon detection of a collision. Reverse Polarity Function In the 10BASE-T mode, the PHY monitors for receiver polarity reversal due to crossed wires and corrects by reversing the signal internally. Collision Detection Function Link Integrity The PHY test for a faulty twisted-pair link. In the absence of transmit data, link test pulses are tranmsitted every 16+/-18ms after the end of the last transmission or link pulse on the twisted pair medium.
BOARD SETUP INFORMATION ISA MODE The following parameters are obtained from the EEPROM as board setup information: REGISTER Configuration Register ETHERNET INDIVIDUAL ADDRESS I/O BASE ADDRESS ROM BASE ADDRESS 8/16 BIT ADAPTER 10BASE-T or AUI INTERFACE INTERRUPT LINE SELECTION Base Register EEPROM WORD ADDRESS IOS Value * 4 (IOS Value *4) + 1 INDIVIDUAL ADDRESS 20-22 hex If IOS2-IOS0=7, only the INDIVIDUAL ADDRESS is read from the EEPROM. Currently assigned values are assumed for the other registers.
REGISTER are written in the EEPROM locations defined by the IOS2-0 pins. DIAGNOSTIC LEDs The following LED drive signals are available for diagnostic and installation aid purposes: The three least significant bits of the CONTROL REGISTER (EEPROM SELECT, RELOAD and STORE) are used to control the EEPROM. Their values are not stored nor loaded from the EEPROM. b) GENERAL PURPOSE REGISTER EEPROM SELECT bit = 1 nTXLED - Activated by transmit activity. nBSELED - Board select LED.
word was written, there will be two or three bytes in the FIFO and a full word can be written into the now even memory address. For example, if an odd pointer value is loaded, first a byte is pre-fetched into the FIFO, and immediately a full word is pre-fetched completing three bytes into the FIFO. If the CPU reads a word, one byte will be left again a new word is pre-fetched.
16 BITS IOS2-0 WORD ADDRESS 000 0h CONFIGURATION REG. 1h BASE REG. 4h CONFIGURATION REG. 5h BASE REG. 8h CONFIGURATION REG. 9h BASE REG. Ch CONFIGURATION REG. Dh BASE REG. 10h CONFIGURATION REG. 11h BASE REG. 14h CONFIGURATION REG. 15h BASE REG. 18h CONFIGURATION REG. 19h BASE REG.
OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ...................................................................................... 0 o C to +70o C Storage Temperature Range ....................................................................................-55o C to +150o C Lead Temperature Range (soldering, 10 seconds) .................................................................. +325o C Positive Voltage on any pin, with respect to Ground ...........................
PARAMETER SYMBO L MIN Low Input Leakage IIL High Input Leakage IP Type Buffers TYP MAX UNITS COMMENTS -10 +10 µA VIN = 0 IIH -10 +10 µA VIN = VCC Input Current ID Type Buffers IIL -150 µA VIN = 0 Input Current I/04 Type Buffer IIH +150 µA VIN = VCC Low Output Level VOL 0.4 V IOL = 4 mA High Output Level VOH 2.4 V IOH = -2 mA Output Leakage I/024 Type Buffer IOL -10 +10 µA VIN = 0 to VCC Low Output Level VOL 0.5 V IOL = 24 mA High Output Level VOH 2.
PARAMETER SYMBO L MIN TYP MAX UNITS COMMENTS 0.5 V IOL = 16 mA +10 µA VIN = 0 to VCC 0.5 V IOL = 16 mA V IOH = -2 mA +10 µA VIN = 0 to VCC 0.5 V IOL = 24 mA +10 95 µA mA OD16 Type Buffer Low Output Level VOL Output Leakage OD162 Type Buffer IOL Low Output Level VOL High Output Level VOH 2.
PARAMETER MIN 10BASE-T Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output: Voltage Source Resistance Transmitter Output DC Offset Transmitter Backswing Voltage to Idle Differential Input Voltage 300 0 ±2 TYP 100 400 ±2.5 ±0.
TIMING DIAGRAMS t1 t2 A[5:0], nREG 0 min t3 nCE1 t4 30 max nOE t5 t6 5 max DATA VALID D[15:0] t1 t2 t3 t4 t5 t6 Parameter Address Access Time nREG Access Time nCE1 Access Time nOE Access Time Output Disable Time from nCE1 high Output disable Time from nOE high Min Typ Max 300 300 300 150 100 Units ns ns ns ns ns 100 ns NOTE: Applies only when nWAIT is asserted by the SMC91C95.
250 min A[5:0], nREG 0 min t4 20 min nCE1 t3 nOE t1 t7 t2 nWE t6 t5 D[15:0 (Din)] t1 t2 t3 t4 t5 t6 t7 Parameter Min Typ Max Units nWE Pulse Width Address/nREG Setup Time to nWE Low Address/nREG Setup Time to nWE High nCE1 Low to nWE High Setup Time Data to nWE High Setup Time Data Hold Time from nWE High Write Recovery Time (Address, nREG Hold from nWE High) 150 30 ns ns 180 ns 180 ns 80 30 30 ns ns ns NOTE: Minimum write pulse width must be met whether or not nWAIT is asserted by th
A[15:0] t18 nMCS t15 t5 t3 nREG t10 t17 t19 t2 t9 nCE t20 t7 t6 t4 t16 nIORD t1 t11 nINPACK t8 t36 nIOIS16 t12 t13 t14 D[15::0] FIGURE 20 - I/O READ TIMING (Table on the following page) 110
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t36 t15 t16 t17 t18 t19 t20 Parameter Address setup before nIORD low nCEI, nCE2 setup before nIORD low nREG setup before nIORD low nIORD low width Address hold from nIORD high nCE1, nCE2 hold following nIORD high nREG hold following nIORD high Address valid to nINPACK low nCE1, nCE2 low to nINPACK low nREG low to nINPACK low nIORD low to nINPACK low Address valid to nIOIs16 valid nIORD low to data valid Data hold following nIORD nIOIS16 delay from address Addr
A[15:0] nMCS t33 t30 t25 t23 nREG t35 t27 t32 t34 t22 nCE1 nCE2 t26 t31 t24 nIOWR t21 t36 nIOIS16 t28 t29 D[15::0] FIGURE 21 - (I/O WRITE TIMING) (Table on the following page) 112
t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 Parameter Address setup before nIOWR low nCE1, nCE2 setup before nIOWR low nREG setup before nIOWR low nIOWR low width Address hold from nIOWR high nCE1, nCE2, hold following nIOWR high nREG hold following nIOWR high Address valid to nIOIS16 valid Data hold following nIOWR Address valid to nMCS low nCE1 low to nMCS low nREG low to nMCS low Address invalid to nMCS high nCE1 high to nMCS high nREG high to nMCS high nIOIS16 delay from address 11
t60 A0-9,A15 t63 t60 valid t61 valid t62 nREG t64 nCE1 t57 nWE nOE t59 t65 t58 D0-7 valid t57 t58 t59 t60 t61 t62 t63 t64 t65 valid Parameter min Write Data Setup to nWE Rising Write Data Hold after nWE Rising nOE Low to Valid Data Address, nREG Setup to nWE Active Address, nREG Hold after nOE Inactive Address, nREG Setup to nOE Active Address, nREG Hold after Control Inactive nCE1 Setup to nWE Rising nCE1 Low to Valid Data 30 9 typ max 40 25 15 25 15 60 0 50 units ns ns ns ns ns ns ns n
t51 A0-9,A15 t52 valid t48 t20 nREG t49 t50 nCE1,nCE t53 nIORD t47 D0-15 valid t46 t46 nINPAC Parameter t46 t47 t48 t20 t49 t50 t51 t52 t53 min nIORD Delay to nREG Low to Control nCE1,nCE2 Setup to Control Cycle Time (No Wait nREG Hold after Control nCE1,nCE2 Hold after Control Address Setup to Control Address Hold after Control nIORD Active to Data typ 0 5 5 185 0 15 25 15 0 FIGURE 23 - PCMCIA CONSECUTIVE READ CYCLES 115 max units 35 ns ns ns ns ns ns ns ns ns 40
t51 t52 A0-9,A15 nREG valid t47 t49 t48 t50 nCE1,nCE2 t20 t54 t55 nIOWR D0-15 valid Parameter min typ max units t47 t48 nREG Low Setup to Control Active nCE1,nCE2 Setup to Control Active 5 5 ns ns t49 t50 nREG Hold after Control Inactive nCE1,nCE2 Hold after Control Inactive 0 15 ns ns t51 t52 Address Setup to Control Active Address Hold after Control Inactive 25 15 ns ns t20 t54 Cycle Time (No Wait States) Write Data Setup to nIOWR Rising 185 30 ns ns t55 Write Data Hold
A0-9,A15 valid valid nREG nCE1 t67 t67 t67 t67 t67 t67 t67 t67 t67 t67 t67 t67 nFCS nWE t66 t66 nFWE nOE Parameter min typ max units t66 nWE to nFWE Delay 0 20 ns t67 Address, nREG, nCE1 Delay to nFCS 0 25 ns FIGURE 25 - PCMCIA ATTRIBUTE MEMORY READ/WRITE (A15=0) 117
nMPWDN] MRINGOUTB t2 t1 t1 t2 Parameter MRINGOUTB Pulse Entering Powerdown MRINGOUTB Pulse Exiting Powerdown Min Typ Max 7.5 Units ms 7.
A0-15 AEN, nSBHE VALID ADDRESS VALID ADDRESS t4 t15 nIOCS16 t3 t20 nIORD t5 t6 VALID DATA OUT D0-15 t3 t4 t5 Z VALID DATA OUT Parameter min Address, nSBHE, AEN Setup to Control Active Address, nSBHE, AEN Hold after Control Inactive nIORD Low to Valid Data 25 20 t6 t15 nIORD High to Data Floating A4-A15, AEN Low, BALE High to nIOCS16 Low t20 Cycle time* typ 185 max Z units ns ns 40 ns 30 25 ns ns ns BALE Tied High IOCHRDY not used - t20 has to be met *Note: The cycle time is def
A0-15 AEN, nSBHE VALID ADDRESS VALID ADDRESS t4 t15 nIOCS16 t3 t20 nIOWR t8 t7 VALID DATA IN D0-15 VALID DATA Parameter t3 t4 t7 t8 t15 t20 min Address, nSBHE, AEN Setup to Control Active Address, nSBHE, AEN Hold after Control Inactive Data Setup to nIOWR Rising Data Hold after nIOWR Rising A4-A15, AEN Low, BALE High to nIOCS16 Low Cycle time* typ max units 25 20 ns ns 30 9 ns ns ns 25 185 ns BALE Tied High IOCHRDY not used - t20 has to be met *Note: The cycle time is defined only for co
A0-15 AEN, nSBHE VALID ADDRESS VALID ADDRESS nIOCS16 t20 nIORD nIOWR t9 Z Z t10 IOCHRDY D0-D15 Z VALID DATA Parameter t9 Control Active to IOCHRDY Low t10 t20 IOCHRDY Low Pulse Width* Cycle time** Z VALID DATA min 100 185 typ max units 15 ns 150 ns ns *Note: Assuming NO WAIT ST = 0 in configuration register and cycle time observed.
A0-15 (ISA) AEN, nSBHE VALID ADDRESS nIOCS16 nIORD t9 Z t18 IOCHRDY Z t19 VALID DATA OUT D0-D15 Parameter min typ max units t9 Control Active to IOCHRDY Low 15 ns t18 IOCHRDY Width when Data is Unavailable at Data Register Valid Data to IOCHRDY Inactive 575 225 ns ns t19 IOCHRDY is used instead of meeting t20 and t43. "No Wait St' bit is 1 - IOCHRDY only negated if needed and only for Data Register access.
A0-15 VALID ADDRESS (ISA) AEN, nSBHE nIOCS16 nIOWR t9 IOCHRDY t18 Z D0-D15 Z VALID DATA IN Parameter min typ max units t9 Control Active to IOCHRDY Low 15 ns t18 IOCHRDY Width when Data Register is Full 425 ns IOCHRDY is used instead of meeting t20 and t44. 'No Wait St' bit is 1 - IOCHRDY only negated if needed and only for Data Register access.
A0-15 (ISA) AEN VALID ADDRESS VALID ADDRESS t3 nIOWR t3 nIORD t7 t8 t5 Z D0-7 Parameter t3 t5 t7 t8 Z VALID DATA OUT VALID DATA IN min Address, nSBHE, AEN Setup to Control Active nIORD Low to Valid Data Data Setup to nIOWR Rising Data Hold after nIOWR Rising typ max 25 40 30 9 units ns ns ns ns FIGURE 32 - 8-BIT MODE REGISTER CYCLES A0-19 ADDRESS VALID t3 t4 nMEMRD Z D0-15 Parameter t3 t4 t16 t17 min Address Setup to Control Active Address Hold after Control Inactive nMEMRD Low to nR
t4 AEN A0-15, nSBHE VALID t1 BALE t2 t15 nIOCS16 t3 nIORD nIOWR Parameter min typ max units t1 Address, nSBHE Setup to BALE Falling 20 ns t2 Address, nSBHE Hold after BALE Falling 20 ns t3 Address, nSBHE, AEN Setup to Control Active 25 ns t4 AEN Hold after Control Inactive 20 t15 A4-A15, AEN Low, BALE High to nIOCS16 Low ns 25 t4 not needed. nIOCS16 not relevant in 8-bit mode.
A0-19 VALID t1 t2 BALE t3 nMEMRD t16 t17 nROM Parameter min typ max units t1 Address Setup to BALE Falling 20 ns t2 Address Hold after BALE Falling 20 ns t3 Address Setup to Control Active 25 ns t16 nMEMRD Low to nROM Low 25 ns t17 nMEMRD High to nROM High 30 ns FIGURE 35 - EXTERNAL ROM READ ACCESS USING BALE 126
EESK EEDO EEDI EECS t21 t21 Parameter t21 min EESK Falling to EEDO, EECS Changing 0 9346 is typically the serial EEPROM used.
EESK EEDO EEDI EECS t21 t21 Parameter t21 min EESK Falling to EEDO, EECS Changing 9346 is typically the serial EEPROM used.
ADDRESS POINTER REGISTER DATA REGISTER nIOWR t44 nIORD IOCHRDY/ nWAIT (Z) Parameter t44 min Pointer Register Reloaded to a Word of Data Prefetched into Data Register typ max 2 * t20 units ns Note: If t44 is not met, IOCHRDY will be negated for the required time. This parameter can be ignored if IOCHRDY is connected to the system.
nTXEN TXD TXCLK t22 t22 Parameter t22 min typ 0 TXD, nTXEN Delay from TXCLK Falling max units 40 ns FIGURE 40 - EXTERNAL ENDEC INTERFACE - START OF TRANSMIT t23 t24 RXD RXCLK nCRS t23 Parameter t23 t24 min 10 30 nCRS, RXD Setup to RXCLK Falling nCRS, RXD Hold after RXCLK Falling typ max units ns ns FIGURE 41 - EXTERNAL ENDEC INTERFACE - RECEIVE DATA (RXD SAMPLED BY FALLING RXCLK) 130
TPETXP t31 t31 TPETXN t32 t32 TPETXDN t33 t33 TPETXDP TWISTED PAIR DRIVERS TXP t34 t34 TXN AUI DRIVERS Parameter t31 t32 t33 t34 min TPETXP to TPETXN Skew TPETXP(N) to TPETXDP(N) Delay TPETXDN to TPETXDP Skew TXP to TXN Skew -1 47 -1 -1.5 typ max units +1 53 +1 1.
1 0 1 0 1 0 1 0 1 0 1 0 1 0 RECP RECN t35 first bit decoded nCRS (internal) t36 1 0 1 0 1 0 TPERXP(N) t37 nCRS (internal) first bit decoded t38 Parameter t35 t36 t37 t38 min typ max units 15 Noise Pulse Width Reject (AUI) Carrier Sense Turn On Delay (AUI) 50 Noise Sense Pulse Width Reject (10BASE-T) 15 450 Carrier Sense Turn On Delay (10BASE-T) 25 70 25 500 30 100 30 550 ns ns ns ns FIGURE 43 - RECEIVE TIMING - START OF FRAME (AUI AND 10BASE-T) 132
last bit b a 1/0 TPERXP TPERXN RECP RECN t39 nCRS (internal) Parameter t39 min 200 Receiver Turn Off Delay typ max units 300 ns FIGURE 44 - RECEIVE TIMING - END OF FRAME (AUI AND 10BASE-T) 133
t40 t41 TPETXP TPETXN last bit b a 1/0 TXP TXN Parameter min t40 Transmit Output High to Idle in Half-Step Mode t41 Transmit Output High before Idle in Half-Step Mode 200 typ max units 800 ns ns FIGURE 45 - TRANSMIT TIMING - END OF FRAME (AUI AND 10BASE-T) 134
COLLP COLLN t42 t43 COL (internal) Parameter min typ max units t42 Collision Turn On Delay 50 ns t43 Collision Turn Off Delay 350 ns FIGURE 46 - COLLISION TIMING (AUI) 135
A2 A1 He E Hd Y D L1 c e 0.08(0.003) M b 0 GAGE PLANE 0.25 L MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 b 0.95 1.00 1.05 0.037 0.039 0.041 0.13 0.18 0.23 0.005 0.007 0.009 c D 0.09 0.20 0.004 0.008 13.90 14.00 14.10 0.547 0.551 0.555 E e Hd He 13.90 14.00 14.10 0.547 0.551 0.555 15.90 16.00 16.10 0.626 0.630 0.634 15.90 16.00 16.10 0.626 0.630 0.634 L 0.45 0.60 0.75 0.018 0.024 0.
300 Kennedy Drive Hauppauge, NY 11788 (516) 435-6000 FAX (516) 231-6004 Circuit diagrams utilizing SMC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies.
