User's Guide

Inforce 67X1User Guide Hardware Specifications
Rev A MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 2
Confidential and Proprietary – SMART Wireless Computing, Inc.
Provided under NDA
2. HARDWARE SPECIFICATIONS
2.1 ARCHITECTURE
The functional diagram of the Inforce 67X1 SOM is shown below.
Figure 1: Block Diagram
SDA845
Octa Core
SOC
IO2
100
Pin
HDR
(P2)
4 lane MIPI-DSI 1
4 lane MIPI-DSI 0
UFS
Primary Boot
JTAG
Debug UART
1
4 lane MIPI-CSI 0
Display & Touch Controls
1
IO1
100
Pin
HDR
(P3)
4 lane MIPI-CSI 2
CCI1 I2C
1
Ver- 0.1
20190116
USB TYPE C WITH DP
USB2 HS HOST
UFS
2.1
Flash Control
1
x1PCIe Gen 3
CAM Controls
1
SDC2 (4bit)
POP
LPDDR4x
RAM
CCI0 I2C
1
WCN3990
2x
MHF4
PCM
UART
Audio
Codec
WCD9340
HPH_L
HPH_R
3x MIC
SLIMBUS
2x Line Out
SLIMBUS/SPKR_I2S
MBHC
VBAT
2
VBAT
2
POWER_ON
VOL +
SPMI
RESET (VOL -)
VREG_S4A_1P8
4xBoot Config
1
PM845
PMI8998
GPS
SDR845
QLINK
USB TYPE C CC Pins
MHF4
PMIC_GPIO
2x CAM MCLKs
1
VREG_L13A_2P95
MI2S
1
APQ_GPIOs
1
1
Pins can be configured as GPIO and some GPIOs can
support multiple BLSP functions (I2C,UART,SPI,UIM)
2
VBAT Power Input
3
VCOIN support 2V to 3.25V
VREG_L21A_2P95
SLIMBUS/SPKR_I2S
VCOIN
3
VBUS_USB_IN
2X DMIC
IO3 100 Pin HDR (P1)
4 Lane MIPI
-CSI 1
2x CAM MCLK
1
VBAT
2
VCOIN
3
APQ_GPIOs
1
VPH
Analog
1x SPKR
PM8005
USB2 SS SIGNALS
WLED
BACKLIGHT
PMIC REGs
2X ANLG MIC
BATTERY
CONTROLS
VBUS
_
USB_IN
x1PCIe Gen
2