AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
41
9634E–AT42–06/12
AT42QT2120
Appendix A. I
2
C-compatible Operation
A.1 Interface Bus
The device communicates with the host over an I
2
C bus. The following sections give an
overview of the bus; more detailed information is available from www.i2C-bus.org. Devices are
connected to the I
2
C bus as shown in Figure A-1. Both bus lines are connected to Vdd via pull-
up resistors. The bus drivers of all I
2
C devices must be open-drain type. This implements a wired
AND function that allows any and all devices to drive the bus, one at a time. A low level on the
bus is generated when a device outputs a zero.
Figure A-1. I
2
C Interface Bus
A.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the
data line must be stable when the clock line is high; the only exception to this rule is for
generating START and STOP conditions.
Figure A-2. Data Transfer
Device 1 Device 2
Device 3 Device n
R1 R2
Vdd
SDA
SCL
SDA
SCL
Data Stable Data Stable
Data Change