AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
36
9634E–AT42–06/12
AT42QT2120
6.6.3 AT42QT2120-MMH – 20-pin VQFN
TITLE
DRAWING NO. GPC
REV.
Package Drawing Contact:
packagedrawings@atmel.com
20M2 ZFC B
20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm,
1.55 x 1.55 mm Exposed Pad, Thermally Enhanced
Plastic Very Thin Quad Flat No Lead Package (VQFN)
10/24/08
15
14
13
12
11
1
2
3
4
5
16 17 18 19 20
10 9 8 7 6
D2
E2
e
b
K
L
Pin #1 Chamfer
(C 0.3)
D
E
SIDE VIEW
A1
y
Pin 1 ID
BOTTOM VIEW
TOP VIEW
A1
A
C
C0.18 (8X)
0.3 Ref (4x)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A 0.75 0.80 0.85
A1 0.00 0.02 0.05
b 0.17 0.22 0.27
C 0.152
D 2.90 3.00 3.10
D2 1.40 1.55 1.70
E 2.90 3.00 3.10
E2 1.40 1.55 1.70
e – 0.45 –
L 0.35 0.40 0.45
K 0.20 – –
y 0.00 – 0.08