AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
31
9634E–AT42–06/12
AT42QT2120
6.4 Timing Specifications
Parameter Description Minimum Typical Maximum Units Notes
T
R
Response time
DI setting
× 16 ms
–
LP mode +
(DI setting
× 16 ms)
ms Under host control
F
QT
Sample frequency 10.5 12.5 – kHz
Modulated
spread-spectrum (chirp)
T
D
Power-up delay to
operate/calibration time
– <230 – ms
Can be longer if burst is
very long.
F
I2C
I
2
C-compatible clock rate – – 400 kHz –
Fm Burst modulation, percentage 15
–% –
RESET pulse width 2 – – µs 2 µs at 1.8 V