AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
28
9634E–AT42–06/12
AT42QT2120
Consideration should be taken on the overall effect on timing when setting Pulse values. A
single pulse takes approximately 90 µs to complete. As all keys are acquired sequentially a
high-bit gain setting will add considerably to the time taken to acquire all channels.
Figure 5-3. Pulse and Scale Settings
Standalone Mode Defaults:
Key 0 Pulse Scale = 0x84
Key 1 Pulse Scale = 0x42
Key 2 – 6 Pulse Scale = 0x00
Comms Mode Defaults: PULSE0 – PULSE3 = 0
SCALE0 – SCALE3 = 0
Table 5-19. Oversample for “n” Bits
Sample Scaling Bits Gained (n)
4
n
2
n
n
1 1 0 (Pulse = 0x0 / Scale = 0x00)
4 2 1 (Pulse = 0x2 / Scale = 0x01)
16 4 2 (Pulse = 0x4 / Scale = 0x02)
64 8 3 (Pulse = 0x6 / Scale = 0x03)
256 16 4 (Pulse = 0x8 / Scale = 0x04)
1024 32 5 (Pulse = 0x0A / Scale = 0x05)
4096 64 6 (Pulse = 0x0C / Scale = 0x06)
16384 128 7 (Pulse = 0x0E / Scale = 0x07)