AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
22
9634E–AT42–06/12
AT42QT2120
5.9 Address 8: Low Power (LP) Mode
LP MODE: This 8-bit value determines the number of 16 ms intervals between key
measurements. Longer intervals between measurements yield a lower power consumption but
at the expense of a slower response to touch.
Default: 1 (16 ms between key acquisitions)
To wake the device from Power-down mode a nonzero LP setting should be written to this
address. The QT2120 can also be reset during power-down mode by writing a nonzero value to
the reset register (address 7).
5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
TOWARD TOUCH DRIFT and AWAY FROM TOUCH DRIFT: Signals can drift because of
changes in Cx and Cs over time and temperature. It is crucial that such drift be compensated for,
else false detections and sensitivity shifts can occur.
Drift compensation (see Figure 5-1) is performed by making the reference level track the raw
signal at a slow rate, but only while there is no detection in effect. The rate of adjustment must
be performed slowly, otherwise legitimate detections could be ignored. The parameters can be
configured in increments of 0.16s.
Table 5-9. LP Mode
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
8LP MODE
Setting Time
0 Power Down
1 16 ms
2 32 ms
3 48 ms
4 64 ms
...254 4.064 s
255 4.08 s
Table 5-10. Toward Touch and Away from Touch Drift
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
9
0 TOWARD TOUCH DRIFT
10
0 AWAY FROM TOUCH DRIFT










