AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
20
9634E–AT42–06/12
AT42QT2120
5.2 Address 0: Chip ID
CHIP ID: Holds the chip ID; always 0x3E.
5.3 Address 1: Firmware Version
MAJOR VERSION: Holds the major firmware version (for example revision 1.5).
MINOR VERSION: Holds the minor firmware version (for example revision 1.5).
5.4 Address 2: Detection Status
CALIBRATE: This bit is set during a calibration sequence.
OVERFLOW: This bit is set if the time to acquire all key signals exceeds 16 ms.
SDET: This bit is set if any of the slider/wheel channels are in detect.
TDET: This bit is set if any of the keys are in detect.
Note: If the slider or wheel is enabled then the SDET bit will be set when it is in detect. Also
the relevant Key Status bit (0 – 2) and TDET will be set. These bits can be ignored if the
SDET bit is set as the slider/wheel takes priority.
A change in these bytes will cause the CHANGE
line to trigger.
86–87 Reference Data 5 Reference data 5 (MSByte) – Reference data 5 (LSByte) R
88–89 Reference Data 6 Reference data 6 (MSByte) – Reference data 6 (LSByte) R
90–91 Reference Data 7 Reference data 7 (MSByte) – Reference data 7 (LSByte) R
92–93 Reference Data 8 Reference data 8 (MSByte) – Reference data 8 (LSByte) R
94–95 Reference Data 9 Reference data 9 (MSByte) – Reference data 9 (LSByte) R
96–97 Reference Data 10 Reference data 10 (MSByte) – Reference data 10 (LSByte) R
98–99 Reference Data 11 Reference data 11 (MSByte) – Reference data 11 (LSByte) R
Table 5-2. Chip ID
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0CHIP ID
Table 5-1. Internal Register Address Allocation (Continued)
Address Use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
Table 5-3. Firmware Version
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 MAJOR VERSION MINOR VERSION
Table 5-4. Detection Status
AddressBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
2
CALIBRATE
OVERFLO
W
– – – – SDET TDET