AT42QT2120 Datasheet
Table Of Contents
- Features
- 1. Pinouts and Schematics
- 2. Overview
- 3. Wiring and Parts
- 4. I2C-compatible Communications (Comms Mode Only)
- 5. Setups
- 5.1 Introduction
- 5.2 Address 0: Chip ID
- 5.3 Address 1: Firmware Version
- 5.4 Address 2: Detection Status
- 5.5 Addresses 3 – 4: Key Status
- 5.6 Address 5: Slider Position
- 5.7 Address 6: Calibrate
- 5.8 Address 7: Reset
- 5.9 Address 8: Low Power (LP) Mode
- 5.10 Address 9 – 10: Toward Touch and Away from Touch Drift (TTD, ATD)
- 5.11 Address 11: Detection Integrator (DI)
- 5.12 Address 12: Touch Recal Delay (TRD)
- 5.13 Address 13: Drift Hold Time (DHT)
- 5.14 Address 14: Slider Options
- 5.15 Address 15: Charge Time
- 5.16 Address 16 – 27: Detect Threshold (DTHR)
- 5.17 Addresses 28 – 39: Key Control
- 5.18 Addresses 40 – 51: Pulse/Scale for Keys
- 5.19 Address 52 – 75: Key Signal
- 5.20 Address 76 – 99: Reference Data
- 6. Specifications
- Appendix A. I2C-compatible Operation
- Associated Documents
- Revision History
2
9634E–AT42–06/12
AT42QT2120
1. Pinouts and Schematics
1.1 Pinouts
1.1.1 20-pin SOIC/TSSOP – Comms Mode
1.1.2 20-pin SOIC/TSSOP – Standalone Mode
KEY8/GPO6
KEY7/GPO5
KEY6/GPO4
KEY5/GPO3
KEY4/GPO2
KEY3/GPO1
KEY2/GPO0
KEY1
KEY0
VSS
RESET
CHANGE
SDA
N/C
KEY11/GPO9
KEY9/GPO7
KEY10/GPO8
VDD
MODE
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
QT2120
OUT3
OUT2
KEY6
KEY5
KEY4
KEY3
KEY2
GUARD
PROX
VSS
RESET
N/C
PXOUT
OUT6
OUT4
OUT5
VDD
MODE
N/C
N/C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
QT2120